Correctable Error Mask Register @0x114
The mask bits in this register control the reporting of correctable errors. For each error type in the Correctable Error Status Register, there is a corresponding bit in this register to mask its reporting. When a mask bit is set the occurrence of the error is not reported (by asserting the CORRECTABLE_ERROR_OUT output).
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/W | Receiver Error Mask [REM] | This bit, when set, masks the reporting of Physical Layer errors. STICKY. | 0x0 |
| 5:1 | R | Reserved [R40] | Reserved | 0x0 |
| 6 | R/W | Bad TP Mask [BTM] | This bit,when set, masks the reporting of an error in response to a 'Bad TLP' received. STICKY. | 0x0 |
| 7 | R/W | Bad DLLP Mask [BDM] | This bit, when set, masks the reporting of an error in response to a 'Bad DLLP' received. STICKY. | 0x0 |
| 8 | R/W | Replay Number Rollover Mask [RNRM] | This bit, when set, masks the reporting of an error in response to a Replay Number Rollover event. STICKY. | 0x0 |
| 11:9 | R | Reserved [R41] | Reserved | 0x0 |
| 12 | R/W | Replay Timer Timeout Mask [RTTM] | This bit, when set, masks the reporting of an error in response to a Replay Timer timeout event. STICKY. | 0x0 |
| 13 | R/W | Advisory Non-Fatal Error Mask [ANEM] | This bit, when set, masks the reporting of an error in response to an uncorrectable error occurence, which is determined to belong to one of the special cases in the PCI Express Base Specification 2.0. STICKY. | 0x1 |
| 14 | R/W | Corrected Internal Error Mask [CIEM] | This bit, when set, masks the reporting of an error in response to a corrected internal error condition. STICKY. | 1'b1 |
| 15 | R/W | Header Log Overflow Mask [HLOM] | This bit, when set, masks the reporting of an error in response to a Header Log register overflow. STICKY. | 1'b1 |
| 31:16 | R | Reserved [R42] | Reserved | 0x0 |