LTSSM Transition Debug Control Register45 @0xf98

This register enables firmware to program two specific LTSSM state transitions to be detected and optionally paused for firmware control.

Table 1. i_ltssm_transition_debug_ctrl_reg45
Bits SW Name Description Reset
0 R/W LTSSM State Transition 4 Freeze Enable [LST4FREN] This bit can be used by firmware to freeze the LTSSM after the programmed LTSSM transition 4 occurs.
  • 1: LTSSM State will be frozen after the programmed transition 4. LTSSM will stay in current_state, by dropping all OS being received.
  • 0: LTSSM State will not be frozen after the programmed transition 4. LTSSM will continue to next legal state.
 0x0
1 R/W LTSSM State Transition 4 Check Enable [LST4CHEN] This bit enables the LTSSM transition 4 check.
  • 1: LTSSM State transition 4 check is enabled.
  • 0: LTSSM State transition 4 check is disabled.
 0x0
8:2 R/W Current LTSSM State 4 [CLTST4] This is the 7-bit Current LTSSM State of LTSSM transition 4 that is required to be checked and optionally paused. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
15:9 R/W Previous LTSSM State 4 [PLTST4] This is the 7-bit Previous LTSSM State of LTSSM transition 4 that is required to be checked. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
16 R/W LTSSM State Transition 5 Freeze Enable [LST5FREN] This bit can be used by firmware to freeze the LTSSM after the programmed LTSSM transition 5 occurs.
  • 1: LTSSM State will be frozen after the programmed transition 5. LTSSM will stay in current_state, by dropping all OS being received.
  • 0: LTSSM State will not be frozen after the programmed transition 5. LTSSM will continue to next legal state.
 0x0
17 R/W LTSSM State Transition 5 Check Enable [LST5CHEN] This bit enables the LTSSM transition 1 check.
  • 1: LTSSM State transition 5 check is enabled.
  • 0: LTSSM State transition 5 check is disabled.
 0x0
24:18 R/W Current LTSSM State 5 [CLTST5] This is the 7-bit Current LTSSM State of LTSSM transition 5 that is required to be checked and optionally paused. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
31:25 R/W Previous LTSSM State 5 [PLTST5] This is the 7-bit Previous LTSSM State of LTSSM transition 5 that is required to be checked. Please refer to the 7-bit LTSSM Encoding table for details. 0x0