Core Feature Control Register @0xe64

This register is for the control of Core Features.

Table 1. i_core_feature_reg

Bits	SW	Name	Description	Reset
0	R	Reserved [R0]	Reserved	0x0
1	R/W	APB Access Clock Shutoff SLVERR select [APBCTRL]	When set the Core will return SLVERR on the APB bus for Read or Writes to Configuration or Local Management registers.	0x0
2	R	Reserved [R2]	Reserved	0x0
31:3	R	Reserved [R30]	Reserved	0x0