Transaction Layer Internal Control Register @0xc94

This register controls internal behavior of Transaction layer of controller. Adjustment of this register is not required for normal operations.

Table 1. tl_internal_control

Bits	SW	Name	Description	Reset
0	R/W	Enable CRS under FLR [ECFLR]	By default controller ignores config request if a function is under going FLR. Setting this bit makes the controller to respond with CRS response.	0x0
1	R/W	Disable Outbound Ordering Check [DOOC]	Ordering between outbound Completions and posted packets are maintainted in transaction layer. This is achieved by blocking Completions if required. Completions arrived after EOP of a posted packet are blocked till that posted packet is transmitted. This Ordering checkis required to conform to the PCIe ordering rules. This ordering check can be disabled by setting this field.	0x1
31:2	R	RSVD	RSVD	30'h00000000