Memory Base, Memory Limit @0x20

This location contains the 16-bit Memory Base Register and the 16-bit Memory Limit Register.

Table 1. i_pcie_mem_base_limit

Bits	SW	Name	Description	Reset
3:0	R	Reserved [R1]	Reserved	0x0
15:4	R/W	Memory Base Register [MBR]	This field can be read and written from the local management APB bus, but its value is not used within the Controller.	12'h0
19:16	R	Reserved [R2]	Reserved	0x0
31:20	R/W	Memory Limit Register [MLR]	This field can be read and written from the local management APB bus, but its value is not used within the Controller.	12'h0