Secondary PCI Express Extended Capability Header Register @0x300
This register contains the PCI Express Extended Capability ID for the Secondary PCI Express Extended Capability, its capability version, and the pointer to the next capability structure. This register is implemented only in the configuration space of PF 0 or RC.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 15:0 | R | PCI Express Extended Capability ID [PECI] | This field is hardwired to the Capability ID assigned by PCI SIG to the Secondary PCI Express Capability | 0x019 |
| 19:16 | R | Capability Version [CV] | Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1, but can be modified independently for each PF from [ the apb bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write]. | 0x1 |
| 31:20 | R | Next Capability Offset [NCO] | Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set. | 12'h900 |