LTR Message Generation Control Register @0x220

This register contains fields for the generation of Latency Tolerance Reporting (LTR) Messages. This register is to be used only when the Controller is configured in the Endpoint mode.

Table 1. i_ltr_msg_gen_ctl_reg
Bits SW Name Description Reset
9:0 R/W Minimum LTR Interval [MLI] This field specifies the minimum spacing between LTR messages transmitted by the Controllerin units of microseconds. The PCI Express Specifications recommend sending no more than two LTR messages within a 500 microsecond interval. The Controller will wait for the minimum delay specified by this field after sending an LTR message, before transmitting a new LTR message.

NOTE: The LINK can be in low power states (L0s and L1) when send LTR Message is trigered. So, the user has to consider the exit latencies while programming this field. It is recommended to program this field with about 2 μs higher than the required interval to account for the L0s/L1 exit latencies.

 0xFA
10 R Send LTR Message [SLM] Setting this bit causes the Controller to transmit an LTR message with the parameters specified in the LTR Snoop/No-Snoop Latency Register (Section 8.4.2.9). This bit is cleared by the Controller on transmitting the LTR message, and stays set until then. Client software must read this register and verify that this bit is 0 before setting it again to send a new message. This field becomes writable when LTR mechanism is enabled in device control-2 register. 0x0
11 R/W Transmit Message on LTR Mechanism Enable Transition [TMLMET] When this bit is set to 1, the Controller will automatically transmit an LTR message whenever the LTR Mechanism Enable bit in the Device Control 2 Register changes from 0 to 1, with the parameters specified in the LTR Snoop/No-Snoop Latency Register. When this bit is 1, the Controller will also transmit an LTR message wheneverthe LTR Mechanism Enable bit is cleared, if the following conditions are both true:
  1. The Controller sent at least one LTR message since the LTR Mechanism Enable bit was last set.
  2. The most recent LTR message transmitted by the Controller had as least one of the Requirement bits set.
The Controller will set the Requirement bits in this LTR message to 0. When this bit 11 is 0, the Controller will not, by itself, send any LTR messages in response to state changes of the LTR Mechanism Enable bit. Client logic may monitor the state of the LTR_MECHANISM_ ENABLE output of the Controller and transmit LTR messages through the master interface, in response to its state changes.		 0x1
12 R/W Transmit Message on Function Power State Change [TMFPSC] When this bit is set to 1, the Controller will automatically transmit an LTR message when all the Functions in the Controller have transitioned to a non-D0 power state, provided that the following conditions are both true:
  1. The Controller sentat least one LTR message since the Data Link layer last transitioned from down to up state.
  2. The most recent LTR message transmitted by the Controller had as least one of the Requirement bits set.
The Controller will set the Requirement bits in this LTR message to 0. When this bit 12 is 0, the Controller will not, by itself, send any LTR messages in response to Function Power State changes. Client logic may monitor the FUNCTION_POWER_STATE outputs of the Controller and transmit LTR messages through the master interface, in response to changes in their states.		 0x1
31:13 R RSVD RSVD 19'h00000