ARI Extended Capability Header Register @0x140
This register is used to enable the Alternate Routing ID interpretation. This register contains the PCI Express Extended Capability ID, the capability version, and the pointer to the next capability structure.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 15:0 | R | PCI Express Extended Capability ID [PECID] | This field is hardwired to the Capability ID assigned by PCI SIG to the ARI Extended Capability (000E hex). | 0x0E |
| 19:16 | R | Capability Version [ARICV] | Specifies the SIG-assigned value for the version of the capability structure. This field is set to 1 by default, but can be modified independently for each Function from the local management bus | 0x01 |
| 31:20 | R | Next Capability Offset [ARINCO] | Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set. | 12'h150 |