Local Interrupt Mask 2 Register @0xd04

This is an extension of the Local Interrupt Mask Register. This register contains a mask bit for each interrupting condition in local_error_status_2_register. Setting the bit to 1 prevents the corresponding condition in the Local Error Status 2 Register from activating the LOCAL_INTERRUPT output.

Table 1. i_local_intrpt_mask_2_reg

Bits	SW	Name	Description	Reset
0	R/W	MSI Mask Cleared [MSIMSKCL]	Mask for MSI Mask Cleared Status.	0x0
1	R/W	MSI Mask Set [MSIMSKSET]	Mask for MSI Mask Set Status.	0x0
2	R/W	MSIX Function Mask Cleared [MSIXMSKCL]	Mask for MSIX Function Mask Set Status.	0x0
3	R/W	MSIX Function Mask Set [MSIXMSKSET]	Mask for MSIX Function Mask Cleared Status.	0x0
4	R/W	Invalid SW Margining Error Mask [ISWMEM]	When the Controller receives a Margining Command from SW in its configuration register, it checks if the command is valid. The error status is logged in local_error_status_2_register. This bit can be used to Mask asserting the LOCAL_INTERRUPT output when the Invalid SW Margining Error Status is set. 1: Error is masked. 0: Error is not masked.	0x0
5	R/W	Invalid PHY Margining Error Mask [IPHYMEM]	When the Controller receives a Margining Command from PHY over the PIPE Interface, it checks if the command is valid. The errorstatus is logged in local_error_status_2_register. This bit can be used to Mask asserting the LOCAL_INTERRUPT output when the Invalid PHY Margining Error Status is set. 1: Error ismasked. 0: Error is not masked.	0x0
6	R/W	Write Ack Wait Timeout Error Mask [WAWTEM]	When a WriteCommitted command is issued by the Controller, the PHY must respond with a Write_Ack within 10ms on the PIPE MessageBus Interface. However, if the Write_Ack is not received within 10ms, the Controller reports Timeout and stops waiting for the write_ack. This bit can be used to Mask asserting the LOCAL_INTERRUPT output upon this 10 ms timeout. 1: Error is masked. 0: Error is not masked.	0x0
7	R/W	Unexpected PHY Response Error Mask [UPREM]	Unexpected PHY Response is detected by Controller if PHY writes to the Margin Status or the Margin NAK bits of RX Margin Status 0 Register when no change in Start Margin or Margin Offset issued by Controller or after the Write Ack Wait Timeout. This bit can be used to Mask asserting the LOCAL_INTERRUPT output upon this error. 1: Error is masked. 0: Error is not masked.	0x0
8	R/W	NFTSTimeout Mask [NFTSTOM]	Mask for NFTS Timeout.	0x0
9	R	Reserved [R9]	Reserved	0x0
10	R	Reserved [R10]	Reserved	0x0
11	R/W	Split Completion Table byte count RAM uncorrectable error mask register [UNCESCBYTE]	Split Completion Table byte count RAM uncorrectable error mask register.	0x0
12	R/W	Split Completion Table Timer RAM uncorrectable error mask register [UNCESCTIMER]	Split Completion Table Timer RAM uncorrectable error mask register.	0x0
13	R/W	Split Completion Table State RAM uncorrectable error mask register [UNCESCSTATE]	Split Completion Table State RAM uncorrectable error mask register.	0x0
14	R/W	Link Equalization Request Interrupt Mask [LEQRQINM]	Mask for Link Equalization Request Interrupt.	1'b1
15	R	Reserved [R15]	Reserved	0x0
16	R/W	LTSSM State Transition Interrupt Mask [LSTINTM]	Mask for LTSSM State Transition Interrupt.	1'b1
17	R/W	FC Timeout Error Mask [FCTEM]	Mask for FC Timeout Error.	1'b0
31:18	R	Reserved [R31]	Reserved	0x0