Advanced Error Capabilities and Control Register @0x118
This location contains a pointer to the first error that is reported in the Uncorrectable Error Status Register.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 4:0 | R | First Error Pointer [FER] | This is a 5-bit pointer to the bit position in the Uncorrectable Error Status Register corresponding to the error that was detected first. When there are multiple bits set in the Uncorrectable Error Status Register, this field informs the software which error was observed first. To prevent the field from being overwritten before software was able to read it, this field is not updated while the status bit pointed by it in the Uncorrectable Error Status Register remains set. After the software clears this status bit, a subsequent error condition that sets any bit in the Uncorrectable Error Status Register will update the First Error Pointer. Any uncorrectable error type, including the special cases where the error is reported using an ERR_COR message, will set the First Error Pointer (assuming the software has reset the error pointed by it in the Uncorrectable Error Status Register). STICKY. F/w will be allowed to write into this first error pointer when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). | 0x0 |
| 5 | R | ECRC Generation Capability [EGC] | This read-only bit indicates to the software that the device is capable of generating ECRC in packets transmitted on the link. This bit is hardwired to 0. The setting of the corresponding bit in the Advanced Error Capabilities and Control Register of PF 0 applies to all Virtual Functions. | 0x0 |
| 6 | R | Enable ECRC Generation [EEG] | Enables the ECRC generation on the transmit side of the core. This bit is hardwired to 0. The setting of the corresponding bit in the Advanced Error Capabilities and Control Register of PF 0 applies to all Virtual Functions. | 0x0 |
| 7 | R | ECRC Check Capability [ECCAP] | This read-only bit indicates to the software that the device is capable of checking ECRC in packets received from the link. This bit is hardwired to 0. This setting of the corresponding bit in the Advanced Error Capabilities and Control Register of PF 0 applies to all Virtual Functions. | 0x0 |
| 8 | R | Enable ECRC Check [ECC] | Setting this bit enables ECRC checking on the receive side of the core. This bit is hardwired to 0. The setting of the corresponding bit in the Advanced Error Capabilities and Control Register of PF 0 applies to all Virtual Functions. | 0x0 |
| 9 | R | Multiple Header Recording Capable [MHRC] | This bit is set when the Function has the capability to log more than one error header in its Header Log Registers. It is hardwired to 0. | 0x0 |
| 10 | R | Multiple Header Recording Enable [MHRE] | Setting this bit enables the Function to log multiple error headers in its Header Log Registers. It is hardwired to 0 | 0x0 |
| 31:11 | R | Reserved [R18] | Reserved | 0x0 |