I/O Base Upper, I/O Limit Upper @0x30

This location contains the upper 16 bits of the I/O Base and I/O Limit Registers.

Table 1. i_pcie_io_base_limit_upper

Bits	SW	Name	Description	Reset
15:0	R	I/O Base Register Upper [IBRU]	This field can be read and written from the local management bus if 32-bit I/O BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.	0x0
31:16	R	I/O Limit Register Upper [ILR]	This field can be read and written from the local management bus if 32-bit I/O BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.	0x0