Uncorrectable Error Status Register @0x104

This register provides the status of the various uncorrectable errors detected by the PCI Express Controller. Software may clear any error bit by writing a 1 into the corresponding bit position. The states of the bits in the Uncorrectable Error Mask Register have no effect on the status bits of this register. The setting of an uncorrectable error status bit causes the Controller to generate an ERR_FATAL message if the corresponding severity bit of the Uncorrectable Error Severity Register is 1. If the severity bit is 0, however, there are two separate ways the error can be processed:
  • In certain cases, the uncorrectable error is treated as an Advisory Non-Fatal Error. These cases are treated as similar to correctable errors, causing the Controller to generate an ERR_COR message instead of an ERR_NONFATAL message. For details on these special cases, refer to Section 6.2.3.2.4 of the PCI Express Base Specifications, Version 1.1.
  • In all other cases, the Controller sends an ERR_NONFATAL message when the error is detected.

In all cases, the sending of the error message can be suppressed by setting the bit corresponding to the error type in the Uncorrectable Error Mask Register. For errors that are not Function-specific, the error status bus is set in the registers belonging to all the Functions associated with the link, but only a single message is generated for the entire link. In the case of certain errors detected by the Transaction Layer, the associated TLP header is logged in the Header Log Registers. All the RW1C bits can also be cleared from the local management bus by writing a 1 into the bit position. If the error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted), f/w will be allowed to write into the AER uncorrectable Error status register.

Table 1. i_uncorr_err_status
Bits SW Name Description Reset
0 R/WOCLR Link Training Error status [LTE] This error indicates that link training is not successful and transition back to detect state. This Status bit is set on any LTSSM transition from Configuration to Detect or Recovery to Detect. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
3:1 R Reserved [R0] Reserved 0x0
4 R/WOCLR Data Link Protocol Error Status [DLPES] This bit is set when the Controller receives an Ack or Nak DLLP whose sequence number does not correspond to that of an unacknowledged TLP or that of the last acknowledged TLP (for details, refer to PCI Express Base Specification 1.1, Section 3.5.2). This error is not Function-specific and is reported by Function 0. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
5 R Surprise down error status [SDES] This error status indicates Link up to Link down event. So Status bit is set upon LINK_DOWN_RESET_OUT event. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
11:6 R Reserved [R1] Reserved 0x0
12 R/WOCLR Poisoned TLP Status [PTS] This bit is set when the Controller receives a poisoned TLP from the link. This error is Function-specific. This error is considered non-fatal by default. The error is reported by sending an ERR_NONFATAL message. The header of the received TLP with error is logged in the Header Log Registers. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
13 R/WOCLR Flow Control Protocol Error Status [FCPES] This bit is set when certain violations of the flow control protocol are detected by the Controller. Controller reports FCPE upon the following conditions:
  1. InitFC/UpdateFC DLLP received which issues more than 2047 cumulative outstanding unused credits to the Transmitter for data payload or 127 for header,
  2. InitFC_P is received with Payload Credits less than 128B,
  3. InitFC_CPL is received with Payload Credits less than 128B.
This error is not Function-specific. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted).		 0x0
14 R/WOCLR Completion Timeout Status [CTS] This bit is set when the completion timer associated with an outstanding request times out. This error is Function-specific. This error is considered non-fatal by default. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
15 R/WOCLR Completer Abort Status [CAS] This bit is set when the Controller has returned the Completer Abort (CA) status to a request received from the link. This error is Function-specific. The header of the received request that caused the error is logged in the Header Log Registers. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
16 R/WOCLR Unexpected Completion Status [UCS] This bit is set when the Controller has received an unexpected Completion packet from the link. This error is not Function-specific. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
17 R/WOCLR Receiver Overflow Status [ROS] This bit is set when the Controller receives a TLP in violation of the receive credit currently available. This error is not Function-specific. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
18 R/WOCLR Malformed TLP Status [MTS] This bit is set when the Controller receives a malformed TLP from the link. This error is not Function-specific. This error is considered fatal by default, and is reported by sending an ERR_FATAL message. The header of the received TLP with error is logged in the Header Log Registers. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
19 R/WOCLR ECRC Error Status [EES] This bit is set when the Controller has detected an ECRC error in a received TLP. This error is not Function-specific. The header of the received TLP with error is logged in the Header Log Registers. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
20 R/WOCLR Unsupported Request Error Status [URES] This bit is set when the Controller has received a request from the link that it does not support. This error is not Function-specific. This error is considered non-fatal by default. In the special case described in Sections 6.2.3.2.4.1 of the PCI Express Specifications, the error is reported by sending an ERR_COR message. In all other cases, the error is reported by sending an ERR_NONFATAL message. The header of the received request that caused the error is logged in the Header Log Registers. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
21 R Reserved [R2] Reserved 0x0
22 R/WOCLR Uncorrectable Internal Error Status [UIE] This bit is set when the Controller has detected an internal uncorrectable error (HAL parity error or an uncorrectable ECC error while reading from any of the RAMs). This bit is also set in response to the client signaling an internal error through the input UNCORRECTABLE_ERROR_IN. This error is not Function-specific. This error is considered fatal by default, and is reported by sending an ERR_FATAL message. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted). 0x0
31:23 R Reserved [R3] Reserved 0x0