Equalization Debug Monitor Status Register @0xe54
All the Dynamic Equalization information is captured in this Register.This is implemented using a synchronous FIFO, which stores all the captured events as sepereate 32 bit entries. Every read increments the read pointer and the client must store the data read. The FIFO can be cleared using the 'Clear all Capture bit in the EQ Debug Monitor Control Register.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 17:0 | R | Coefficients [EQCOEFF] |
|
0x0 |
| 21:18 | R | Preset [EQPRE] |
|
0x0 |
| 22 | R | Preset Valid [EQPREVD] | 1: Preset Valid, Indicates [21:18] is valid.
|
0x0 |
| 23 | R | Coefficient Reject [COEFFREJ] |
|
0x0 |
| 29:24 | R | Direction Feedback [DIRFED] | EP Ph2/RC Ph3: Stores Direction Change Feedback or Preset feedback Transmitted to Remote Device. Bit-22, EQPREVD, indicates if this is a Preset feedback or Direction Change Feedback. EP Ph3/RC Ph2: Reserved | 0x0 |
| 31:30 | R | Equalization Phase [EQPHASE] | Equalization Phase during Capture
|
0x0 |