Prefetchable Limit Upper @0x2c

This location contains the upper 32 bits of the Prefetchable Limit Register. This register is enabled by programming the Root Complex BAR configuration register in the Local Management space.

Table 1. i_pcie_prefetch_limit_upper

Bits	SW	Name	Description	Reset
31:0	R	Prefetchable Limit Register Upper [PLRU]	This field can be read and written from the local management APB bus if 64-bit prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.	32'h0