Revision ID and Class Code Register @0x8
This register contains the Revision ID and Class Code associated with the device incorporating the PCIe Controller.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R | Revision ID [RID] | Assigned by the manufacturer of the device to identify the revision number of the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 8'h0 |
| 15:8 | R | Programming Interface Byte [PIB] | Identifies the register set layout of the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x0 |
| 23:16 | R | Sub-Class Code [SCC] | Identifies a sub-category within the selected function. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 8'h0 |
| 31:24 | R | Class Code [CC] | Identifies the function of the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 8'h0 |