16 GT/s Lane Equalization Control Register 0 @0x9e0
This register contains the Upstream Port 16.0GT/s Transmitter Preset for lanes 0, 1, 2, and 3, received from the Downstream Port during the 16GT/s Link Equalization procedure.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 3:0 | R | Reserved [R0] | Reserved | 0x0 |
| 7:4 | R | Lane 0 Upstream Port 16.0GT/s Transmitter Preset [UPTP016] | 16.0GT/s Lane 0 Transmitter Preset value received from the downstream port during 16GT/s Link Equalization. | 0xf |
| 11:8 | R | Reserved [R8] | Reserved | 0x0 |
| 15:12 | R | Lane 1 Upstream Port 16.0GT/s Transmitter Preset [UPTP116] | 16.0GT/s Lane 1 Transmitter Preset value received from the upstream device. | 0xf |
| 19:16 | R | Reserved [R16] | Reserved | 0x0 |
| 23:20 | R | Lane 2 Upstream Port 16.0GT/s Transmitter Preset [UPTP216] | 16.0GT/s Lane 2 Transmitter Preset value received from the upstream device. | 0xf |
| 27:24 | R | Reserved [R24] | Reserved | 0x0 |
| 31:28 | R | Lane 3 Upstream Port 16.0GT/s Transmitter Preset [UPTP316] | 16.0GT/s Lane 3 Transmitter Preset value received from the upstream device. | 0xf |