Physical Layer Configuration Register 2 @0x54

This register controls various LTSSM related capabilities.

Table 1. i_pl_config_2_reg
Bits SW Name Description Reset
0 R/W Link Training Enable Software Control [LK_TRN] This bit is AND'ed with the input LINK_TRAINING_ENABLE strap to enable Link Training. 1'b1
2:1 R/W Detect Quiet Minimum Delay Control [DQMDC] As per PCIe specification, All Receivers must meet the the Z-RX-DC specification for 2.5 GT/s within 1ms of entering Detect.Quiet LTSSM substate. The LTSSM must stay in this substate until the ZRX- DC specification for 2.5 GT/s is met. This register field can be used to program the minimum time that LTSSM waits on entering Detect.Quiet state.
  • 00 : 0us minimum wait time in Detect.Quiet state.
  • 01 : 100us minimum wait time in Detect.Quiet state.
  • 10 : 1ms minimum wait time in Detect.Quiet state.
  • 11 : 2ms minimum wait time in Detect.Quiet state.
 2'b01
3 R Reserved [R3] Reserved 0x0
7:4 R/W RX Electrical Idle Min Delay [RXEIMD] Minimum time that the Receive logic will stay in Idle after receiving EIOS, before checking for RX electrical idle exit sequences such as EIEOS/TS1/FTS. This is used to prevent spurious receive data from causing an exit after EIOS is received. Register value indicates the minimum delay in units of 16 ns. All received data will be ignored for the programmed Min Delay. Default value is 3. 4'b0011
8 R/W Disable Extended Speed Change Delay [DESCD] After changing the speed, the LTSSM waits for phy_status response from PHY. This field is used to control the maximum time the LTSSM waits for the response.
  • 0 : 4 ms maximum time LTSSM waits in Recovery.Speed for PHY STATUS response
  • 1 : 1 ms maximum time LTSSM waits in Recovery.Speed for PHY STATUS response
 1'b0
14:9 R/W Disable Enhanced TS Symbol Consecutive Check [DTSSCC] The Controller LTSSM checks symbols of the received TS OS to match to determine if the TS are consecutive. This field can be used to turn off this check.
  • Bit-0:
    • 0 : Enable symbol 1 consecutive check in TS OS
    • 1 : Disable symbol 1 consecutive check
  • Bit-1:
    • 0 : Enable symbol 2 consecutive check in TS OS
    • 1 : Disable symbol 2 consecutive check
  • Bit-2:
    • 0 : Enable symbol 3 consecutive check in TS OS
    • 1 : Disable symbol 3 consecutive check
  • Bit-3:
    • 0 : Enable symbol 4 consecutive check in TS OS
    • 1 : Disable symbol 4 consecutive check
  • Bit-4:
    • 0 : Enable symbol 5 consecutive check in TS OS
    • 1 : Disable symbol 5 consecutive check
  • Bit-5:
    • 0 : Enable symbol 6,7,8,9 consecutive checks in TS in all states at Gen3 and higher and Symbol 6 consecutive checks in all states at Gen1,2
    • 1 : Enable symbol 6,7,8,9 consecutive checks in TS only in Equalization states at Gen3 and higher
 0x0
15 R Reserved [R15] Reserved 0x0
16 R/W Disable Rate Identifier ConsecutiveCheck [DRICC] The Data Rate supported by remote end is advertised in the received TS1/TS2. The advertised data rates are captured by the Controller in eight consecutive TS1s/TS2s in various LTSSM states. This field can be used to disable waiting for eight consecutive TS1/TS2 and capture based on every TS1/TS2 in Recovery and Configuration.
  • 0 : Wait for eight consecutive TS1/TS2 and capture advertised data rates
  • 1 : Capture advertised data rates from every TS1/TS2 in Recovery and Configuration States
 1'b0
17 R/W Disable Electrical Idle Data Blank [DEIDB] During entry into RX Electrical Idle, an EIOS is received. Controller is required to ignore any receive data after EIOS. The receive data after EIOS is blanked by the Controller by default. Setting this bit to 1 disables data blanking and allows spurious receive data after EIOS. This bit must be 0 for functional modes.
  • 0 : Blank RX Data after EIOS, till a valid electrical idle exit
  • 1 : Do not blank RX Data after EIOS
 1'b0
31:18 R Reserved [R18] Reserved 0x0