Correctable Error Status Register @0x110

This register provides the status of the various correctable errors detected by the PCI Express Controller. Software may clear any error bit by writing a 1 into the corresponding bit position. The states of the bits in the Correctable Error Mask Register have no effect on the status bits of this register. The setting of a correctable error status bit causes the Controller to generate an ERR_COR error message to the Root Complex if the error is not masked in the Correctable Error Mask Register. For errors that are not Function-specific, the error status bus is set in the registers belonging to all the Functions associated with the link, but only a single message is generated for the entire link. Header logging of received TLPs does not apply to correctable errors. All the RW1C bits can also be cleared from the local management bus by writing a 1 into the bit position. F/w will be allowed to write into AER correctable error status field when error emulation emulation feature is enabled (i.e., if bit 12 of Debug MUX Control 3 register is asserted).

Table 1. i_corr_err_status
Bits SW Name Description Reset
0 R/WOCLR Receiver Error Status [RES] This bit is set when an error is detected in the receive side of the Physical Layer of the Controller (e.g. a bit error or coding violation). This bit is set upon any of the following errors:
  1. PHY reported 8B10B error, Disparity Error, Elastic Buffer Overflow Error, Underflow Error
  2. GEN3 TLP, DLLP Framing Errors
  3. OS Block Received Without EDS
  4. Data Block Received After EDS
  5. Illegal OS Block After EDS
  6. OS Block Received After SKIP OS
  7. OS Block Received After SDS
  8. Sync Header Error
  9. Loss of Gen3 Block Alignment
This error is not Function-specific. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted		 0x0
5:1 R Reserved [R12] Reserved 0x0
6 R/WOCLR Bad TP Status [BTS] This bit is set when an error is detected in a received TLP by the Data Link Layer of the Controller. The conditions causing this error are:
  • an LCRC error
  • the packet terminates with EDB symbol, but its LCRC field does not equal the inverted value of the calculated CRC.
This error is not Function-specific. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted)		 0x0
7 R/WOCLR Bad DLLP Status [BDS] This bit is set when an LCRC error is detected in a received DLLP, and no errors were detected by the Physical Layer. This error is not Function- specific. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
8 R/WOCLR Replay Number Rollover Status [RNRS] This bit is set when the replay count rolls over after three re-transmissions of a TLP at the Data Link Layer of the Controller. This error is not Function-specific STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
11:9 R Reserved [R13] Reserved 0x0
12 R/WOCLR Replay Timer Timeout Status [RTTS] This bit is set when the replay timer in the Data Link Layer of the Controller times out, causing the Controller to retransmit a TLP. This error is not Function-specific. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
13 R/WOCLR Advisory Non- Fatal Error Status [ANFES] This bit is set when an uncorrectable error occurs, which is determined to belong to one of the special cases described in Section 6.2.3.2.4 of the PCI Express 2.0 Specifications. This causes the Controller to generate an ERR_COR message in place of an ERR_NONFATAL message. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
14 R/WOCLR Corrected Internal Error Status [CIES] This bit is set when the Controller has detected an internal correctable error condition (a correctable ECC error while reading from any of the RAMs). This bit is also set in response to the client signaling an internal error through the input CORRECTABLE_ERROR_IN. This error is not Function-specific. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
15 R/WOCLR Header Log Overflow Status [HLOS] This bit is set on a Header Log Register overflow, that is, when the header could not be logged in the Header Log Register because it is occupied by a previous header. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
31:16 R Reserved [R14] Reserved 0x0