Result Tab

The Result tab, which is under the Dashboard, shows all of the reports and files that result from compilation. Double-click on any file to view it in the Code Editor. Additionally, it shows a summary table of the resources used. You can right-click the items in the Result tab to open a context-sensitive menu with shortcut actions. If you double-click a filename, the file opens in the Code Editor (default) or the editor you set in your Efinity preferences (see Setting General Tool Preferences).

Tip: In Efinity® v2020.2 and higher you can resize the Result tab. Grab the blank space between the Result tab and the Console and drag to resize.

Table 1. Compilation Files and ReportsThe software generates these files when you run the flow.
Category	File	Description
Synthesis	<project>.map.v	Post-mapping netlist file for simulation.
	<project>.map.core.v	Post-mapping core netlist file for simulation with the unified design flow.
	<project>.map.peri.v	Post-mapping interface netlist file for simulation with the unified design flow.
	<project>.map.rpt	Synthesis report file; gives a summary of the resources your design uses.
	<project>.map.out	Messages output to the Console during synthesis; includes any synthesis warnings or errors.
	<project>.res.csv	Provides the resource usage for all of the modules in the design.
Placement	<project>.place	Detailed placement report.
	<project>.place.rpt	Resource summary report.
	<project>.place.out	Messages output to the Console during placement.
Routing	<project>.pnr.rpt	Provides the resource summary for inputs, outputs, clocks, LEs, memory, and multipliers (Trion) or DSP Blocks (Titanium and Topaz).
	<project>.route.rpt	Routing report.
	<project>.timing.rpt	Static timing analysis report.
	<project>.route.out	Messages output to the Console during routing.
Bitstream	<project>.hex	Use this file to program in SPI active or passive mode.
	<project>.bit	Use this file for JTAG programming.
	<project>.pgm.out	Messages output to the Console during bitstream generation.

Table 2. Interface Designer FilesThe Interface Designer generates these files when you click the Generate Interface Output Files button and when you do a full compile.
File	Description
<project>.interface.csv	Constrains the FPGA design pins used in the interface between the core and the periphery.
<project>.pt.rpt	Interface Design report file with details of the blocks used, I/O banks, global connections, clock region usage, GPIO and dual-function configuration pins used, etc.
<project>.pinout.rpt	Has the board design pinout with pin number, signal name, pin name, I/O bank, etc. in a nicely formatted text file format.
<project>.pinout.csv	Pinout report file formatted as .csv.
<project>.pt_timing.rpt	Timing report for the Trion®, Topaz, and Titanium interface logic.
<project>.pt.sdc	Template SDC file to constrain the FPGA design pins based on the interface configuration.
<project>_or.ini	Contains option register information the Programmer uses.
<project>_template.v	Template Verilog HDL file defining the FPGA design pins based on the interface configuration.
<project>.unified.isf	ISF file that creates design instances and set their properties based on the interface logic discovered by synthesis in the unified design flow.
<project>.auto_asg.isf	ISF file with interface logic automatically assigned to resources in the unified design flow.
<project>.peri_rtl.v	Interface netlist file (blocks inferred by synthesis) for simulation in the unified design flow.
<project>.peri_pt.v	Interface netlist file (blocks from Interface Designer) for simulation in the unified design flow.