Fixed-Point Handling (16.10)

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.fixed_pkg.all;

Entity test is
Port (
       s1   : in ufixed(21 downto -2);
       s2   : in ufixed(20 downto -3);
       sum  : out ufixed(22 downto -3);
       prod : out ufixed(42 downto -5)
);
end test;

Architecture behave of test is
Begin
sum <= s1 +S2;
prod <= S1*S2;	
end behave;