Example: --infer-clk-enable

The --infer-clk-enable synthesis option infers the flip-flop clock enable signal from control logic. This option has three effort levels, or you can disable it.

For example, if you choose effort level 1, this code:

always @(posedge clk) begin
  if (e1 | e2) q <= d;
end

infers or (e1,e2) as the CE pin of a flop with d in the D pin and q in the Q pin.

In a more complex case, this code:

always @(posedge clk) begin
  if (e1) q <= d1;
  else (e2) q <= d2;
end

does not result in an inferred clock enable.

With the effort level 3 option, which is the default, the synthesis tool traces multiplexer connections to look for a loop back to the Q pin of the flip-flop. If the tracing is successful, the software extracts the condition pins of the multiplexer path to form the clock enable signal. So in our complex example previously, the software infers or (e1, e2) inferred as the clock enable. The level 3 option reduces the number of LUTs by about 4-5% compared to the level 1 option.