Simulation Models

The Efinix core primitive models are located in the directory <installation directory>/sim_models/verilog.

Table 1. Core Primitive Simulation Models

Primitive	Description	Trion	Titanium	Topaz	Filename
EFX_ADD	Simple Full Adder				efx_add.v
EFX_COMB4	Simple 4-Input LUT ROM plus Simple Adder				efx_comb4.v
EFX_DPRAM5K	5 Kbit True-Dual-Port RAM Block				efx_dpram5k.v
EFX_DPRAM10	10 Kbit True-Dual-Port RAM Block				efx_dpram10.v
EFX_DSP12	Quad-Mode 4 x 4 DSP Block				efx_dsp12.v
EFX_DSP24	Dual-Mode 8 x 8 DSP Block				efx_dsp24.v
EFX_DSP48	Full Function DSP Block				efx_dsp48.v
EFX_FF	D Flip-flop with Clock Enable and Set/Reset Pin				efx_ff.v
EFX_GBUFCE	Global Clock Buffer				efx_gbufce.v
EFX_LUT4	Simple 4-Input LUT ROM				efx_lut4.v
EFX_MULT	18 x 18 Multiplier				efx_mult.v
EFX_RAM_5K	5 Kbit RAM Block				efx_ram_5k.v
EFX_RAM10	10 Kbit RAM Block				efx_ram10.v
EFX_SRL8	8-Bit Shift Register				efx_srl8.v

The Efinix interface primitive models are located in the directory <installation directory>/pt/sim_models/verilog

Table 2. Interface Primitive Simulation ModelsAlthough additional model files are located in the /pt/sim_models/verilog directory, only the ones listed in this table are supported.

Primitive	Description	Trion	Titanium	Topaz	Filename
EFX_CLKOUT	Clock Output Buffer				EFX_CLKOUT.v
EFX_FPLL_V1	Fractional PLL				EFX_FPLL_V1.v
EFX_GPIO_V1	Basic GPIO				EFX_GPIO_V1.v
EFX_GPIO_V2	GPIO with Double Data I/O Function				EFX_GPIO_V2.v
EFX_GPIO_V3	HVIO and HSIO Used as Single-Ended GPIO				EFX_GPIO_V3.v
EFX_GPIO_DIFF_V3	HVIO and HSIO Used as Differential GPIO				EFX_GPIO_DIFF_​V3.v
EFX_IBUF	Single-Ended Input Buffer				EFX_IBUF.v
EFX_IDDIO	Input Double Data I/O Register				EFX_IDDIO.v
EFX_IOREG	Single-Ended Bi-Directional Register				EFX_IOREG.v
EFX_IO_BUF	Single-Ended Bi-Directional Buffer				EFX_IO_BUF.v
EFX_IREG	Single-Ended Input Register				EFX_IREG.v
EFX_JTAG_CTRL	JTAG Interface				EFX_JTAG_CTRL.v
EFX_JTAG_V1	JTAG User TAP Interface				EFX_JTAG_V1.v
EFX_OBUF	Single-Ended Output Buffer				EFX_OBUF.v
EFX_ODDIO	Output Double Data I/O Register				EFX_ODDIO.v
EFX_OREG	Single-Ended Output Register				EFX_OREG.v
EFX_OSC_V1	Oscillator				EFX_OSC_V1.v
EFX_OSC_V3	Oscillator				EFX_OSC_V3.v
EFX_PLL_V1	Simple PLL				EFX_PLL_V1.v
EFX_PLL_V2	Advanced PLL				EFX_PLL_V2.v
EFX_PLL_V3	Full-Featured PLL				EFX_PLL_V3.v
EFX_LVDS_RX_V1	LVDS Reciever				EFX_LVDS_RX_V1.v
EFX_LVDS_RX_V2	LVDS Receiver				EFX_LVDS_RX_V2.v
EFX_LVDS_TX_V1	LVDS Transmitter				EFX_LVDS_TX_V1.v
EFX_LVDS_TX_V2	LVDS Transmitter				EFX_LVDS_TX_V2.v
EFX_LVDS_BIDIR_V2	LVDS Transmitter/Receiever				EFX_LVDS_BIDIR_​V2.v