Clock Synchronizers

If you have asynchronous clock groups and want to transfer data between them, you need to add synchronizing registers (also known as synchronizers). Synchronizers are register chains in the receiving clock domain that capture data from the sending domain. They prevent meta-stable events from propagating into the receiving clock domain.

To designate a register as a synchronizer, use the async_reg synthesis attribute.

When async_reg is true, synthesis does not perform optimization to reduce, merge, or duplicate these registers. During place and route, the software keeps these registers close together to improve synchronization between asynchronous clock domains.

Verilog HDL:
(* async_reg = "true" *) reg [1:0] x;
VHDL:
attribute async_reg: boolean;
attribute async_reg of x : signal is true;