syn_ramstyle

You apply this attribute to RAM signals:

• The block_ram value assigns the signals to block RAM.
• The registers value assigns the signals to registers.

Verilog HDL:

(* syn_ramstyle = "block_ram" *) reg [DWIDTH-1:0] mem [DEPTH-1:0];
(* syn_ramstyle = "registers" *) reg [DWIDTH-1:0] mem [DEPTH-1:0];

VHDL:

attribute syn_ramstyle: string;
attribute syn_ramstyle of mem : signal is "block_ram";