Trion DDR Properties

Table 1. DDR General Properties
API Name GUI Name Values
CLK_NAME Clock Instance Instance name
CLK_PIN Clock Pin Name PLL output clock 0 name
CLK_RESOURCE Clock Resource PLL resource. Read only.
MEMORY_TYPE Memory Type DDR3, LPDDR2, LPDDR3
NAME Instance Name Instance Name
RESOURCE DDR Resource None, DDR_0
Table 2. DDR Configuration Properties
API Name GUI Name Values
DDR3 LPDDR3 LPDDR2
ADV_DENSITY_EN Enable Advanced Density Setting 0, 1 0, 1 0, 1
COLUMN_WIDTH Column Width 0 - 99 0 - 99 0 - 99
DQ_WIDTH DQ Width x16 x16 x16
MEMORY_SPEED Speed Grade 800D, 800E, 1066E, 1066F, 1066G 800, 1066 400, 533, 667, 800, 1066
MEMORY_WIDTH Width x8, x16 x16 x16
MEMORY_DENSITY Density 1G, 2G, 4G, 8G 4G, 8G 256M, 512M, 1G, 2G, 4G
PRESET Preset1 153, 155, 157, 159, 161, 163, 165, 167, 169, 171 200 175, 177, 179, 181, 183
ROW_WIDTH Row Width 0 - 99 0 - 99 0 - 99
Table 3. DDR Advanced Options (FPGA Settings) Properties
API Name GUI Name Values
DDR3 LPDDR3 LPDDR2
FPGA_INPUT FPGA Input Termination (Ohm) 20, 30, 40, 60, 120 120, 240, OFF 120, OFF
FPGA_OUTPUT FPGA Output Termination (Ohm) 34, 40 34, 40, 48, 60, 80 34, 40, 48, 60, 80, 120
Table 4. DDR Advanced Options (Memory Mode Register Settings) Properties
API Name GUI Name Values
DDR3 LPDDR3 LPDDR2
ASR Auto Self-Refresh Manual, Auto
BL Burst Length 8 8
CL CAS Latency 5-14
CWL CAS Write Latency 5-12
DQ_ODT DQ Termination Disable, RZQ/1, RZQ/2, RZQ/4
MOUTPUT Output Termination RZQ/6, RZQ/7
OUT_DRIVE_STR Output Drive Strength (Ohm) 34.3, 34.3 pull-down / 40 pull-up, 34.3 pull-down / 48 pull-up, 40, 40 pull-down / 48 pull-up, 48 34.3, 40, 48, 60, 80, 120
PRECHARGE_PD DLL Precharge Power Down On, Off
READ_BURST_TYPE Read Burst Type Interleaved, Sequential Interleaved, Sequential
RL/WL Read/Write Latency RL=3/WL=1, RL=6/WL=3, RL=8/WL=4, RL=9/WL=5 RL=3/WL=1, RL=4/WL=2, RL=5/WL=2, RL=6/WL=3, RL=7/WL=4, RL=8/WL=4
RTT_WR Memory Dynamic ODT Off, RZQ/2, RZQ/4
RTT_NOM Input Termination Off, RZQ/2, RZQ/4, RZQ/6, RZQ/8, RZQ/12
SRT Self-Refresh Temperature Normal, Extended
Table 5. DDR Advanced Options (Memory Timing Settings) Properties
API Name GUI Name Values
TFAW tFAW, Four Bank Active Window (ns) 20.0 - 100.0
TRAS tRAS, Active To Precharge Command Period (ns) 20.0 - 100.0
TRC tRC, Active To Active Or REF Command Period (ns) 20.0 - 100.0
TRCD tRCD, Active To Read Or Write Delay (ns) 2.0 - 50.0
TREFI tREFI, Average Periodic Refresh Interval (ns) 2.0 - 30.0
TRFC tRFC, Refresh to Active Or Refresh to Refresh Delay (ns) 90.0 - 960.0
TRP tRP, PRecharfe Cpmmand Period (ns) 8.0 - 50.0
TRRD tRRD, Active to Active Command Period (ns) 2.0 - 50.0
TRTP tRTP, Internal Read To Precharge Delay (ns) 2.0 - 50.0
TWTR tWTR, Internal Write to Read Command Delay (ns) 2.0 - 100.0
Table 6. DDR Advanced Options (Controller Settings) Properties
API Name GUI Name Values
CONTROL_MAP Controller To Memory Address Mapping ROW-COL_HIGH-BANK-COL_LOW, ROW-BANK-COL, BANK-ROW-COL
CONTROL_REFRESH_EN Enable Self-Refresh Controls No, Yes
POWER_DOWN_EN Enable Auto Power Down Off, Active, Precharge
Table 7. DDR Advanced Options (Gate Delay Tuning Settings) Properties
API Name GUI Name Values
GCOARSE_DELAY Gate Coarse Delay Tuning 0 - 5
GDELAY_OVERRIDE_EN Enable Gate Delay Override 0, 1
GFINE_DELAY Gate Fine Delay Tuning 0 - 255
Table 8. DDR Control Properties
API Name GUI Name Values
CONTROL_TYPE Type Disable, Calibration, User Reset, Reset and Calibration
RESET_PIN Master Reset Pin Name Pin name
SCL_IN_PIN SCL Input Pin Name Pin name
SDA_IN_PIN SDA Input Pin Name Pin name
SDA_OUT_PIN SDA Output Pin Name Pin name
SEQ_RESET_PIN Sequencer Reset Pin Name Pin name
SEQ_START_PIN Sequencer Start Pin Name Pin name
Table 9. DDR AXI Propertiesn is 0 or 1
API Name GUI Name Values
AXIn_CLK_INPUT_PIN AXI Clock Input Pin Name Pin name
AXIn_CLK_INVERT_EN Invert AXI Clock Input 0, 1
AXIn_AID_BUS Address ID [7:0] Bus Name Pin name
AXIn_AREADY_PIN Address Ready Pin Name Pin name
AXIn_AVALID_PIN Address Valid Pin Name Pin name
AXIn_ABUS Address [31:0] Bus Name Pin name
AXIn_ABURST_LEN_BUS Burst Length [7:0] Bus Name Pin name
AXIn_ABURST_SIZE_BUS Burst Size [2:0] Bus Name Pin name
AXIn_ABURST_BUS Burst Type [1:0] Bus Name Pin name
AXIn_ALOCK_BUS Lock Type [1:0] Bus Name Pin name
AXIn_AOP_TYPE_PIN Operation Type Pin Name Pin name
AXIn_BID_BUS Response ID [7:0] Bus Name Pin name
AXIn_BREADY_PIN Response Ready Pin Name Pin name
AXIn_BVALID_PIN Write Response Valid Pin Name Pin name
AXIn_RDATA_BUS Read Data Bus Name Pin name
AXIn_RID_BUS Read ID Bus Name Pin name
AXIn_RLAST_PIN Read Last Pin Name Pin name
AXIn_RREADY_PIN Read Ready Pin Name Pin name
AXIn_RRESP_BUS Read Response Bus Name Pin name
AXIn_RVALID_PIN Read Valid Pin Name Pin name
AXIn_WDATA_BUS Write Data Bus Name Pin name
AXIn_WID_BUS Write ID Bus Name Pin name
AXIn_WLAST_PIN Write Last Pin Name Pin name
AXIn_WREADY_PIN Write Ready Pin Name Pin name
AXIn_WSTRB_BUS Write Strobes Bus Name Pin name
AXIn_WVALID_PIN Write Valid Pin Name Pin name
TARGETn_EN Enable Target n 0, 1
1 Use get_preset() command to obtain preset names.