syn_romstyle

You apply this attribute to ROM signals:

• The block_rom value assigns the signals to block ROM.
• The logic value assigns the signals to logic.

Verilog HDL:

(* syn_romstyle = "block_rom" *) reg [DWIDTH-1:0]    mem [DEPTH-1:0];
(* syn_romstyle = "logic" *) reg [DWIDTH-1:0]        mem [DEPTH-1:0];

VHDL:

attribute syn_romstyle: string;
attribute syn_romstyle of mem : signal is "block_rom";