PMA Direct Property Reference

These PMA Direct block properties are only applicable to Titanium FPGAs with transceivers. Refer to the data sheet for which packages have transceivers.

Table 1. Base Properties
API Name GUI Name Values
NAME Instance Name Instance name
RESOURCE PMA Direct Resource Resource
PRESET1 Preset
1.25G-100.0MHz-20Bits
1.25G-100.0MHz-40Bits
1.485G-148.5MHz-20Bits
1.485G-148.5MHz-40Bits
2.376G-148.5MHz-20Bits
2.376G-148.5MHz-40Bits
2.5G-100.0MHz-20Bits
2.5G-100.0MHz-40Bits
2.7G-100.0MHz-20Bits
2.7G-100.0MHz-40Bits
2.97G-148.5MHz-20Bits
2.97G-148.5MHz-40Bits
3.125G-156.25MHz-20Bits
3.125G-156.25MHz-40Bits
4.752G-148.5MHz-20Bits
4.752G-148.5MHz-40Bits
5.0G-100.0MHz-20Bits
5.0G-100.0MHz-40Bits
5.0G-156.25MHz-20Bits
5.0G-156.25MHz-40Bits
5.4G-100.0MHz-20Bits
5.4G-100.0MHz-40Bits
5.94G-148.5MHz-20Bits
5.94G-148.5MHz-40Bits
6.25G-100.0MHz-20Bits
6.25G-100.0MHz-40Bits
6.375G-100.0MHz-40Bits
6.75G-100.0MHz-40Bits
8.0G-100.0MHz-40Bits
8.1G-50.0MHz-40Bits
8.1G-75.0MHz-40Bits
8.1G-90.0MHz-40Bits
9.504G-148.5MHz-40Bits
10.0G-100.0MHz-40Bits
10.0G-156.25MHz-40Bits
10.3125G-156.25MHz-40Bits
10.3125G-156.25MHz-64Bits
11.88G-148.5MHz-40Bits2
12.5G-100.0MHz-40Bits2
12.5G-156.25MHz-40Bits2
12.5G-156.25MHz-64Bits2
Table 2. Control Register Properties
API Name GUI Name Values
PHY_PMA_L_NID__PHY_PMA_XCVR_​CTRL__PHY_PMA_XCVR_CTRL_0 Rx Polarity Inversion 0, 1
PHY_PMA_L_NID__PHY_PMA_XCVR_​CTRL__PHY_PMA_XCVR_CTRL_8 Tx Polarity Inversion 0, 1
PMA_L_NID__DET_STANDEC_A_PREG__​DRVCTRL_EDGEBOOST_EN_MODE0_PREG Tx Edge Boost Enable 0, 1
PMA_L_NID__DRVCTRL_BOOST_PREG__​DRVCTRL_EDGEBOOST_TUNE_PREG Edge Boost Tune 0x0:0x3
PMA_L_NID__DRVCTRL_BOOST_PREG__​DRVCTRL_AMPBOOST_EN_PREG Tx Amplitude Boost Enable 0, 1
PMA_L_NID__DRVCTRL_BOOST_PREG__​DRVCTRL_AMPBOOST_TUNE_PREG Amplitude Boost Tune 0x0:0x7
SS_RAW_BUNDLE_MODE_LANE_NID Bonding Mode x1, x2, x4, x8
SS_RAW_MODE_LANE_NID Mode Rx FIFO,
Tx FIFO, Rx FIFO,
Tx FIFO, Rx Register
SS_RAW_EQ_EVAL_LANE_NID Equalization Evaluation 0, 1
SS_RAW_TX_EQ_MODE_LANE_NID Tx equalization mode 3 taps FIR filter
Deemphasis
SS_RAW_MAIN_C0_LANE_NID Main C0 0x0:0x3f
SS_RAW_PRE_C_LANE_NID Pre C-1 0x0:0x3f
SS_RAW_POST_C_LANE_NID Post C+1 0x0:0x3f
SS_RAW_DEEM_LANE_NID Deemphasis 3.5 dB, 6dB, Off
Table 3. Clock and Reset Properties
API Name GUI Name Values
RAW_SERDES_TX_CLK_PIN Interface Transmit Clock Pin Name Pin name
TX_CLK_CONN_TYPE Transmit Clock Input Connection Type gclk, rclk
RAW_SERDES_RX_CLK_PIN Interface Receive Clock Pin Name Pin name
RX_CLK_CONN_TYPE Receive Clock Input Connection Type gclk, rclk
PCS_RST_N_RX_PIN PCS Receive Reset Pin Name Pin name
PCS_RST_N_TX_PIN PCS Transmit Reset Pin Name Pin name
PHY_RESET_N_PIN PHY Lane Reset Pin Name Pin name
CLK_RESOURCE_EN Used as Clock Resource 0, 1
PCR_BYPASS_CMN_READY Enable Quad Common Ready (PMA_CMN_READY) Bypass 0, 1
Table 4. Control Properties
API Name GUI Name Values
PMA_TX_ELEC_IDLE_PIN PMA Transmit Electrical Idle Pin Name Pin name
Table 5. Data Interface Properties
API Name GUI Name Values
RXD_PIN Receive Data 63:0 Bus Name Bus name
TXD_PIN Transmit Data 63:0 Bus Name Bus name
Table 6. Error and Status Properties
API Name GUI Name Values
PHY_INTERRUPT_PIN PHY Interrupt Pin Name Pin name
Table 7. Power Up Properties
API Name GUI Name Values
PMA_RX_SIGNAL_DETECT_PIN PMA Receiver Signal Detect Pin Name Pin name
PMA_XCVR_PLLCLK_EN_PIN Link PLL Clock Enable Pin Name Pin name
PMA_XCVR_PLLCLK_EN_ACK_PIN Link PLL Clock Enable Acknowledge Pin Name Pin name
PMA_XCVR_POWER_STATE_ACK_PIN Link Power State Acknowledge 3:0 Bus Name Bus name
PMA_XCVR_POWER_STATE_REQ_PIN Link Power State Request 3:0 Bus Name Bus name
Table 8. Common Properties: APB
API Name GUI Name Values
APB_EN Enable Advanced Peripheral Bus 1, 0
USER_APB_CLK_PIN APB Clock Pin Name Pin name
USER_APB_CLK_INVERT_EN Invert APB Clock Pin 1, 0
USER_APB_PADDR_PIN APB Address 23:0 Bus Name Bus name
USER_APB_PENABLE_PIN APB Enable Pin Name Pin name
USER_APB_PRDATA_PIN APB Read Data 31:0 Bus Name Bus name
USER_APB_PREADY_PIN APB Ready Pin Name Pin name
USER_APB_PSEL_PIN APB Select Pin Name Pin name
USER_APB_PWDATA_PIN APB Write Data 31:0 Bus Name Bus name
USER_APB_PWRITE_PIN APB Write Pin Name Pin name
Table 9. Common Properties: Error and Status
API Name GUI Name Values
PMA_CMN_READY_PIN PHY Ready Pin Name Pin name
Table 10. Common Properties: Configuration
API Name GUI Name Values
COMMON_INST_NAME Common Instance Name Read only3
Table 11. Common Properties: Reference Clock
API Name GUI Name Values
PLL_LC_CONN Common PLL Connection Refclk 0,
Refclk 0 and 1
SS_REFCLK_FREQ Reference Clock 0 Frequency (MHz) 19.19 - 156.28
PIPE_CONFIG_CMN__CONFIG_REG_2​__PMA_CMN_REFCLK_SEL Reference Clock 0 Source External
PIPE_CONFIG_CMN__CONFIG_REG_2​__PMA_CMN_REFCLK_TERMEN Enable 50 Ω to ground on-die termination for REFCLK0 0, 1
SS_REFCLK_FREQ_2 Reference Clock 1 Frequency (MHz) 19.19 - 156.28
PIPE_CONFIG_CMN__CONFIG_REG_2​__PMA_CMN_REFCLK1_SEL Reference Clock 1 Source External
PIPE_CONFIG_CMN__CONFIG_REG_2​__PMA_CMN_REFCLK1_TERMEN Enable 50 Ω to ground on-die termination for REFCLK1 0, 1
SS_REFCLK_ONBOARD_OSC Reference clock from on-board crystal 0, 1
REFCLK_SEL Reference Clock Select Refclk 0,
Refclk 1
MODE Mode Preset, Custom
SS_RAW_DATA_RATE_LANE_NID Data Rate (Gbps) 1.25 - 12.5
SS_RAW_SERDES_WIDTH_LANE_NID SerDes Width (Bits) 20 bits, 32 bits, 40 bits, 64 bits
SS_REFCLK_FREQ Reference Clock 0 Frequency (MHz) 19.19:156.28
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK_SEL Reference Clock 0 Source External, Internal
REF_CLK_INTERNAL_SRC Internal Source Core, PLL
PMA_CMN_REFCLK_CORE_PIN PMA Core Reference Clock Pin Name
SS_REFCLK_FREQ_2 Reference Clock 1 Frequency (MHz) 19.19:156.28
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK1_SEL Reference Clock 1 Source External, Internal
REF_CLK1_INTERNAL_SRC Internal Source Core, PLL
PMA_CMN_REFCLK1_CORE_PIN PMA Core Reference Clock Pin Name
Table 12. Common Properties: Clock and Reset
API Name GUI Name Values
PHY_RESET_EN Enable PHY Quad Reset Pin 0, 1
PHY_CMN_RESET_N_PIN PHY Quad Reset Pin Name Pin name
1 For the PRESET values, the software ignores the case (values are case-insensitive), ignores white-space, and accepts values with or without the units. For example, all of the following values are acceptable:
  • 1.25-100.0-20
  • 1.25 G- 100.0 Mhz - 20bits
  • 1.25-100.0-20bits
2 This data rate is only supported in C4, I4, C4L, I4L speed grades.
3 You specify this name with the create_block() function.