Defining Clocks

Clock sources can come from interface blocks like PLLs or oscillators, or they can come from your board to the core through GPIO pins. You define and identify clocks using the create_clock and create_generated_clock constraints.

The create_clock constraint defines a real or virtual clock with a specific duty cycle and period (ns). Each target can have multiple clocks associated with it.

Define a Clock

This constraint creates a clock, clk1, with a period of 10 ns:

create_clock  -period 10  -name clk1 [get_ports clk1]

Tip: As you may remember from physics class, the clock period is the inverse of the frequency (T = 1/f). So if you want to specify the period in ns for a 50 MHz clock frequency, you use this calculation:

T = (1/50 MHz) * 1000 Hz/MHz = 20 ns

The -waveform option lets you define the clock's rising and falling edges.

Define a Clock with a Waveform

This example defines a clock with a 10 ns period and 50/50 duty cycle, but the first rising clock edge is phase shifted 25% to start at 2.5 ns.

create_clock -period 10.00 -waveform {2.50 7.50} -name clk1 [get_ports clk1]

The create_generated_clock constraint defines a relationship between an internally generated clock and its source clock. This constraint only supports the divide_by, multiply_by, duty_cycle, and invert options.

Creating Clocks

The following example shows the constraints for the base clock clk and the internally generated clock clkdiv2.

create_clock -name clk -period 10 [get_ports clk]
create_generated_clock -source clk -divide_by 2 clkdiv2

Virtual clocks are clocks that are not assigned to a timing node. They are used to represent off-chip clocks and are used in set_input_delay and set_output_delay constraints.

For more details, refer to: