Using the set_clock_groups Constraint

Use this constraint to define the relationship between the clocks and generated clocks you defined. Typically, only clocks from the same source are related to each other. For example, clock outputs from the same PLL or clocks from a single clock pin. Any other clocks should be specified as unrelated.

Unrelated clock groups can be exclusive or asynchronous.

  • Exclusive clock groups do not operate at the same time as each other.
  • Asynchronous clock groups have no timing relationship between them, for example, clocks driven from two independent PLLs.

You use the -exclusive or -asynchronous options to define how to treat the clock groups. The Efinity® software treats both options identically, but some third-party EDA tools use these constraints when checking for proper clock domain crossing logic. Therefore, it is a good idea to use the correct option for the relationship.

To illustrate how to set constraints using set_clock_groups, consider a design with four clocks, clk1, clk2, clk3, and clk4. After design analysis, you determine that clk1 and clk2 are related to each other and clk3 and clk4 are unrelated to all others. There are two ways to use the set_clock_groups constraint, both of which are correct.

Use a Single Constraint

The first method is to define the clocks and groups with a single constraint:
set_clock_groups -exclusive -group {clk1 clk2} -group {clk3} -group {clk4}

This constraint defines the relationship between clocks clk1, clk2, clk3, and clk4. If you later add an additional clock, clk5, and do not update the constraints, the software assumes that clk5 is synchronous to all other clocks.

Use Separate Constraints

The second method is to use separate constraints for each group:
set_clock_groups -exclusive -group {clk1 clk2}
set_clock_groups -exclusive -group {clk3}
set_clock_groups -exclusive -group {clk4}

In this case, each set_clock_groups constraint only specifies one group, which tells the software that the clocks in a given group are asynchronous to all others. With this method, if you later add clk5, the software would consider it to be asynchronous to clk1, clk2, clk3, and clk4.

It can be tempting to use the second method in case you forget a clock or add one later. However, whichever method you choose, Efinix recommends that you always include constraints for each clock in your design and that you update your SDC file when you add clocks.