Generated Files

The IP Manager generates these files and directories:

• <module name>_define.vh—Contains the customized parameters.
• <module name>_tmpl.v—Verilog HDL instantiation template.
• <module name>_tmpl.vhd—VHDL instantiation template.
• <module name>.v—IP source code.
• settings.json—Configuration file.
• <kit name>_devkit—Has generated RTL, example design, and Efinity® project targeting a specific development board.
• Testbench—Contains generated RTL and testbench files.

In Efinity software v2025.2 and higher, the IP Manager can generate synthesized files for out-of-context (OOC) synthesis flows. See "Out-of-Context Synthesis" in the Efinity Synthesis User Guide for more details. The generated OOC files are:

• <module name>.ooc.vdb—Synthesized IP core.
• <module name>.stub.v—Defines the boundaries of the synthesized circuit. The software uses this file when synthesizing your top-level design that includes the OOC archive.