Viewing Place-and-Route Results

You view place-and-route results in the Console pane, in the Result pane, and in the Floorplan Editor.

  • The Console displays messages generated during compilation. For example, if the design has too many I/O pins to fit in the target device, compilation will stop and the Console will show the error message.
  • The Result pane shows the output and report files for each stage in the flow. Additionally, the Report pane displays a table of the interface resources the design uses; if your design has a debug core, it also shows a table of resources used by the debugger.
    Note: Double-click on a file name to open it in the Efinity Code Editor.
  • After you have run a project through synthesis, placement, and routing, you can open the Floorplan Editor tool to see a representation of the tiles in the FPGA and the placement of logic, memory, I/O, and other blocks. Click the Floorplan Editor icon in the main toolbar to open the Floorplan Editor.
Tip: Detach the Floorplan Editor tool from the main Efinity window for better viewing.
Figure 1. Floorplan Editor
Note: If you have disabled auto-loading, you cannot view place-and-route results in the Floorplan Editor or Timing Browser, or use the Tcl console. To enable these tools, click the Load Place and Route Data button in the main window. Refer to Auto-Load Place-and-Route Data for details.
Notice: Refer to the Efinity Trion Tutorial for more information on how to use the Floorplan Editor.