Export JTAG Operations at the Command Line

The Efinity software includes a Python script you can use to export JTAG operations of the JTAG bridge to an SVF file at the command line.

When using the export_bitstream_flashloaderv3.py script, you must connect to the FPGA board using a download cable.

export_bitstream_flashloaderv3.py [--help] --jtag_bridge_file JTAG_BRIDGE_FILE [--freq FREQ]
    [--start_address START_ADDRESS] [--target TARGET] [--chip_num CHIP_NUM]
    [--jcf JCF] [--url URL] [--verify_method VERIFY_METHOD] input_file output_file
Table 1. export_bitstream_flashloaderv3.py Positional Arguments
Argument Description
input_file Image file source.
output_file Image file destination.
Table 2. export_bitstream_flashloaderv3.py Options
Option (Long) Option (Short) Input Description
--help -h None Show help.
--jtag_bridge_file N/A File path The file path of the JTAG-to-SPI Bridge bitstream.
--freq N/A Number JTAG frequency.
Default: 6e6
--start_address N/A Hex number Starting flash address for flash read and write operations, excluding 0x.
--target N/A lower, upper, both Target flash. both is used for the x8 mode.
--chip_num N/A Number 1-based device position in the JTAG chain.
Default: 1
--jcf N/A File path JTAG chain file in XML format. Not needed if there is only one device.
--url -u URL FTDI URL (see Identifying FTDI URLs).
--verify_method N/A none, onchipx1, onchipx2, onchipx4 The method used to verify the downloaded bitstream.
Default: onchipx2 (On-chip hash calculation with SPI x2 mode)

Export JTAG Bridge Operations to an SVF File

%EFINITY_HOME%\bin\python3
%EFINITY_HOME%\pgm\bin\efx_pgm\export_bitstream_flashloaderv3.py bitstream.hex
    output.svf --jtag_bridge_file %EFINITY_HOME%\pgm\fli\titanium\u006A0A79.bit
Note: Load the JTAG Bridge bitstream into the FPGA before using the exported SVF file. The output file of the export_bitstream_flashloaderv3.py script does not include the JTAG Bridge bitstream.

Run the export_bitstream_flashloaderv3 Python Script

To create an SVF file:
  1. Generate your bitstream file.
  2. Run the export_bitstream_flashloaderv3.py script. It will download the JTAG bridge into the FPGA, then program the SPI flash with the bitstream file. Only the SPI flash programming actions of the JTAG operations will be captured.
Note: If you are using an Efinix development board, you can connect to the board using a USB cable. If not, use an external download cable.
To use the created SVF file:
  1. Download the JTAG bridge into the FPGA.
  2. Execute the created SVF file to program the SPI flash with your project bitstream.