skip_ram_init

This attribute applies to an instantiated block RAM instance. When set to 1 or true, synthesis instructs the bitstream generation module to skip including default RAM initialization values to reduce the bitstream size. When the FPGA is configured, the RAM content is not initialized and must be written before being read.

Verilog HDL:

(*skip_ram_init = 'true'*) EFX_RAM10 dut (...);

VHDL:

attribute skip_ram_init : boolean;
attribute skip_ram_init of u0 : label is true;