Clock Latency

The source clock latency represents the time it takes to get from the clock source on the board to the global clock tree on the FPGA. This delay includes the board delay, buffer delay, and any PLL delay (including PLL compensation delay, which is negative, see AN 042: Working with PLLs).

Most of the time you do not need to use set_clock_latency. However, it is required when you want to constrain external signals to core registers to capture the latency effect of the clock signal transferring onto the FPGA.

You need to calculate the delay based on the GPIO mode, PLL mode, and any board delays.

The Efinity software v2023.2 and higher creates a template for the set_clock_latency constraint in the <project>.pt.sdc file. The following topics explain how to calculate clock latency for GPIO and PLL clocks and how to use the template to create the SDC constraints.