Titanium and Topaz DDR Properties

Table 1. DDR General Properties
API Name GUI Name Values
CLK_NAME Clock Instance Instance name. Read only.
CLK_PIN Clock Pin Name PLL output clock 0 name. Read only.
CLK_RESOURCE Clock Resource PLL resource. Read only.
CLKIN_SEL Clock CLKIN 0, CLKIN 1, CLKIN 2
MEMORY_TYPE Memory Type LPDDR4, LPDDR4x
NAME Instance Name Instance Name
RESOURCE DDR Resource None, DDR_0
Table 2. DDR Configuration Properties
API Name GUI Name Values
LPDDR4 LPDDR4x
DQ_WIDTH DQ Width x16, x32 x16, x32
MEMORY_DENSITY Density 2G, 3G 4G, 6G, 8G, 12G, 16G 2G, 3G 4G, 6G, 8G, 12G, 16G
PHYSICAL_RANK Physical Rank 1, 2 1, 2
Table 3. DDR Advanced Options (FPGA Settings) Properties
API Name GUI Name Values
LPDDR4 LPDDR4x
VREF_RANGE VREF Range Range 0, Range 1 Range 0, Range 1
VREF_SETTING VREF Settings (% of VDDQ)
Range 0:
5.40 - 38.42
Range 1:
11.90 - 48.22
Range 0:
11.60 - 49.70
Range 1:
21.20 - 59.30
DQ_PD_DRV_STRENGTH DQ Pull-Down Drive Strength (Unit: Ohm) 34.3, 40, 48, 60, 80, 120, 240 34.3, 40, 48, 60, 80, 120, 240
DQ_PD_ODT DQ Pull-Down ODT (Unit: Ohm) 34.3, 40, 48, 60, 80, 120, 240, Hi-Z 34.3, 40, 48, 60, 80, 120, 240, Hi-Z
DQ_PU_DRV_STRENGTH DQ Pull-Up Drive Strength (Unit: Ohm) 34.3, 40, 48, 60, 80, 120, 240 34.3, 40, 48, 60, 80, 120, 240
DQ_PU_ODT DQ Pull-Up ODT (Unit: Ohm) 34.3, 40, 48, 60, 80, 120, 240, Hi-Z 34.3, 40, 48, 60, 80, 120, 240, Hi-Z
Table 4. DDR Advanced Options (Memory Mode Register Settings) Properties
API Name GUI Name Values
BL Burst Length BL = 16 Sequential,
BL = 16 or 32 Sequential,
BL = 32 Sequential
CA_ODT_CS0 CA Bus Receiver On-Die Termination for CS0 Disable, RZQ/1, RZQ/2, RZQ/3, RZQ/4, RZQ/5, RZQ/6
CA_ODT_CS1 CA Bus Receiver On-Die Termination for CS1 Disable, RZQ/1, RZQ/2, RZQ/3, RZQ/4, RZQ/5, RZQ/6
DBI_READ_EN Enable DBI Read 0: Disable read data bus inversion
1:Enable read data bus inversion
DBI_WRITE_EN Enable DBI Write 0: Disable write data bus inversion
1:Enable write data bus inversion
DQ_ODT_CS0 DQ Bus Receiver On-Die Termination for CS0 Disable, RZQ/1, RZQ/2, RZQ/3, RZQ/4, RZQ/5, RZQ/6
DQ_ODT_CS1 DQ Bus Receiver On-Die Termination for CS1 Disable, RZQ/1, RZQ/2, RZQ/3, RZQ/4, RZQ/5, RZQ/6
PDDS_CS0 Pull-Down Drive Strength for CS0 RFU, RZQ/1, RZQ/2, RZQ/3, RZQ/4, RZQ/5, RZQ/6
PDDS_CS1 Pull-Down Drive Strength for CS1 RFU, RZQ/1, RZQ/2, RZQ/3, RZQ/4, RZQ/5, RZQ/6
CA_VREF_RANGE CA VREF Setting Range Selection RANGE [0], RANGE [1]
CA_VREF_SETTING CA VREF Settings (% of VDD2) RANGE [0]:
10 - 30 (step: 0.4)
RANGE [1]:
22 - 42 (step: 0.4)
DQ_VREF_RANGE DQ VREF Setting Range Selection RANGE [0], RANGE [1]
DQ_VREF_SETTING DQ VREF Settings (% of VDDQ) RANGE [0]:
10 - 30 (step: 0.4)
RANGE [1]:
22 - 42 (step: 0.4)
CK_ODTE_CS0 CK ODT CS0 Enabled for Non-terminating Rank Override Disabled, Override Enabled
CK_ODTE_CS1 CK ODT CS1 Enabled for Non-terminating Rank Override Disabled, Override Enabled
CS_ODTE_CS0 CS ODT CS0 Enabled for Non-terminating Rank Override Disabled, Override Enabled
CS_ODTE_CS1 CS ODT CS1 Enabled for Non-terminating Rank Override Disabled, Override Enabled
CA_ODTD_CS0 CA ODT CS0 Termination Disable Obeys ODT_CA Bond Pad, Disabled
CA_ODTD_CS1 CA ODT CS1 Termination Disable Obeys ODT_CA Bond Pad, Disabled
Table 5. DDR Advanced Options (Memory Timing Settings) Properties
API Name GUI Name Values
TFAW tFAW, Four Bank Active Window (ns) 40.0 - 100.0
TRAS tRAS, Active To Precharge Command Period (ns) 42.0 - 100.0
TRCD tRCD, Active To Read Or Write Delay (ns) 18.0 - 100.0
TRRD tRRD, Active to Active Command Period (ns) 10.0 - 100.0
TRTP tRTP, Internal Read To Precharge Delay (ns) 7.5 - 100.0
TWTR tWTR, Internal Write to Read Command Delay (ns) 10.0 - 60.0
TCCD tCCD, CAS-to-CAS Delay Integer 8 - 31
TCCDMW tCCDMW, CAS-to-CAS Delay Masked Write Integer 32 - 63
TPPD tPPD, Precharge to Precharge Delay (cycles) Integer 4 - 7
TRPAB tRPab, Row Precharge Time (All Banks) (ns) 21.0 - 100.0
TRPPB tRPpb, Row Precharge Time (Single Bank) (ns) 18.0 - 100.0
TSR tSR, Minimum Self Refresh Time (ns) 15.0 - 100.0
TWR tWR, Write Recovery Time (ns) 18.0 - 60.0
Table 6. DDR Config Controller Properties
API Name GUI Name Values
CFG_DONE_PIN Config Controller Done Pin Pin name
CFG_RESET_PIN Config Controller Reset Pin Pin name
CFG_SEL_PIN Config Controller Select Pin Pin name
CFG_START_PIN Config Controller Start Pin Pin name
Table 7. DDR Controller Status Properties
API Name GUI Name Values
CTRL_CLK_PIN Controler Status Clock Pin Pin name
CTRL_CLK_INVERT_EN Invert Controller Status Clock Pin name
CTRL_INT_PIN Controller Detects Interrupt Pin Name Pin name
CTRL_MEM_RST_VALID_PIN Controller Has Reseted Pin Name Pin name
CTRL_REFRESH_PIN Controller Refresh Command Pin Name Pin name
CTRL_CKE_PIN Delayed CKE From Controller Pin name
CTRL_BUSY_PIN Controller Busy PIn Name Pin name
CTRL_CMD_Q_ALMOST_FULL_PIN Command Queue Full Pin Name Pin name
CTRL_DP_IDLE_PIN Data Path Idle Pin Name Pin name
CTRL_PORT_BUSY_PIN Port Busy Reading Data Pin Name Pin name
Table 8. DDR AXI Propertiesn is 0 or 1
API Name GUI Name Values
TARGETn_EN Enable Target n 0, 1
AXIn_DATA_WIDTH Data Width n 512
AXIn_CLK_INPUT_PIN AXI Clock Input Pin Name Pin name
AXIn_CLK_INVERT_EN Invert AXI Clock Input 0, 1
AXIn_ARSTN_PIN AXI Reset Pin Name Pin name
Table 9. DDR AXI (Read Address Channel) Propertiesn is 0 or 1
API Name GUI Name Values
AXIn_ARID_BUS Address ID [5:0] Bus Name Pin name
AXIn_ARREADY_PIN Address Ready Pin Name Pin name
AXIn_ARVALID_PIN Address Valid Pin Name Pin name
AXIn_ARLEN_BUS Burst Length [7:0] Bus Name Pin name
AXIn_ARSIZE_BUS Burst Size [2:0] Bus Name Pin name
AXIn_ARBURST_BUS Burst Type [1:0] Bus Name Pin name
AXIn_ARLOCK_PIN Lock Type Bus Name Pin name
AXIn_ARQOS_PIN QoS Identifier for Read Transaction Pin Name Pin name
AXIn_ARADDR_BUS Read Address [32:0] Bus Name Pin name
AXIn_ARAPCMD_PIN Read Auto-Precharge Pin Name Pin name
Table 10. DDR AXI (Write Address Channel) Propertiesn is 0 or 1
API Name GUI Name Values
AXIn_AWID_BUS Address ID [5:0] Bus Name Pin name
AXIn_AWREADY_PIN Address Ready Pin Name Pin name
AXIn_AWVALID_PIN Address Valid Pin Name Pin name
AXIn_AWLEN_BUS Burst Length [7:0] Bus Name Pin name
AXIn_AWSIZE_BUS Burst Size [2:0] Bus Name Pin name
AXIn_AWBURST_BUS Burst Type [1:0] Bus Name Pin name
AXIn_AWLOCK_PIN Lock Type Bus Name Pin name
AXIn_AWCACHE_BUS Memory Type [3:0] Bus Name Pin name
AXIn_AWQOS_PIN QoS Identifier for Write Transaction Pin Name Pin name
AXIn_AWADDR_BUS Write Address [32:0] Bus Name Pin name
AXIn_AWALLSTRB_PIN Write All Strobes Asserted Pin Name Pin name
AXIn_AWAPCMD_PIN Write Auto-Precharge Pin Name Pin name
AXIn_AWCOBUF_PIN Write Coherent Bufferable Selection Pin Name Pin name
Table 11. DDR AXI (Write Response Channel) Propertiesn is 0 or 1
API Name GUI Name Values
AXIn_BID_BUS Response ID [7:0] Bus Name Pin name
AXIn_BREADY_PIN Response Ready Pin Name Pin name
AXIn_BVALID_PIN Write Response Valid Pin Name Pin name
AXIn_BRESP_BUS Write Response [1:0] Bus Name Pin name
Table 12. DDR AXI (Read Data Channel) Propertiesn is 0 or 1
API Name GUI Name Values
AXIn_RDATA_BUS Read Data Bus Name Pin name
AXIn_RID_BUS Read ID Bus Name Pin name
AXIn_RLAST_PIN Read Last Pin Name Pin name
AXIn_RREADY_PIN Read Ready Pin Name Pin name
AXIn_RRESP_BUS Read Response Bus Name Pin name
AXIn_RVALID_PIN Read Valid Pin Name Pin name
Table 13. DDR AXI (Write Data Channel) Propertiesn is 0 or 1
API Name GUI Name Values
AXIn_WDATA_BUS Write Data Bus Name Pin name
AXIn_WLAST_PIN Write Last Pin Name Pin name
AXIn_WREADY_PIN Write Ready Pin Name Pin name
AXIn_WSTRB_BUS Write Strobes Bus Name Pin name
AXIn_WVALID_PIN Write Valid Pin Name Pin name
Table 14. Pin Swizzling Properties
API Name GUI Name Values
PIN_SWIZZLE_EN Enable Package Pin Swapping 0, 1
PIN_SWIZZLE_DQM0 DQ/DM Pin Swizzle Group0 STRING: "DQ[0],DQ[1],DQ[2],DQ[3],DQ[4],DQ[5],DQ[6],DQ[7],DM[0]"1
PIN_SWIZZLE_DQM1 DQ/DM Pin Swizzle Group1 STRING: "DQ[8],DQ[9],DQ[10],DQ[11],DQ[12],DQ[13],DQ[14],DQ[15],DM[1]"1
PIN_SWIZZLE_DQM2 DQ/DM Pin Swizzle Group2 STRING: "DQ[16],DQ[17],DQ[18],DQ[19],DQ[20],DQ[21],DQ[22],DQ[23],DM[2]"1
PIN_SWIZZLE_DQM3 DQ/DM Pin Swizzle Group3 STRING: "DQ[24],DQ[25],DQ[26],DQ[27],DQ[28],DQ[29],DQ[30],DQ[31],DM[3]"1
PIN_SWIZZLE_CA Address Pin Swizzle STRING:"CA[0],CA[1],CA[2],CA[3],CA[4],CA[5]"1
1 The sequence of items in the strings determines the swizzling of pin. Left most item is the smallest index and the right most is the biggest.