<project>_template.v

In GUI Result pane > Interfaces menu
In file system <project>/outflow
Created by Interface Designer when generating constraints
Design source? No

The Interface Designer creates this file when you generate constraints. This file provides the a template Verilog HDL file defining the FPGA design pins based on the interface configuration. You can use this file as the starting point for the Efinity synthesis top-level target. The port list in the file matches the Interface Designer-generated SDC constraint file. To use this file:

  1. Save the file with a different name to the directory where you keep your source files, such as your project directory.
  2. Add the new file to you project as a design file.
  3. Change the top-level entity in the Efinity project to be the module name given in this file. For example, if the module name is pt_demo, change the top-level entity name to pt_demo in Project Editor > Design tab > Top Module/Entity.
  4. Add the design content.