About the <project>.pt_timing.rpt File

This report shows the timing for your design's interface blocks. When you generate constraints in the Interface Designer, the software creates this file in the outflow directory.

Clocks can come from several sources: PLL, GPIOs, MIPI RX Lane, MIPI RX PHY, JTAG.

The PLL Timing Report shows details about the clocks generated by PLLs in the interface, including the clock period, any phase shift, and whether the clock is inverted. This data matches the create_clock SDC template. The report also shows the PLL compensation delay. Clock Latency and Constraining I/O describe how to use the data.

---------- 1. PLL Timing Report (begin) ----------
+--------+--------+---------+----------+----+-----------------+--------------+--------------+
|   PLL  |Resource|Reference|Core Clock| FB |      Core       |      PLL     |      PLL     |
|Instance|        |  Clock  |Reference |Mode|  Feedback Pin   | Compensation | Compensation |
|        |        |         |   Pin    |    |                 |Delay Max (ns)|Delay Min (ns)|
+--------+--------+---------+----------+----+-----------------+--------------+--------------+
|  pll   |PLL_TR0 | external|          |core|clk~CLKOUT~40~482|    4.310     |      2.155   |
+--------+--------+---------+----------+----+-----------------+--------------+--------------+

+-------+-------------+-----------------------+
| Clock | Period (ns) | Phase Shift (degrees) |
+-------+-------------+-----------------------+
|  clk  |   10.0000   |           0           |
+-------+-------------+-----------------------+

The GPIO Timing Report and HSIO GPIO Timing reports give timing information about the GPIO or HSIO blocks used in your design. The data is grouped by non-registered and registered blocks.

For non-registered blocks, the Max value is the worst case (slowest corner) and the Min is the best case (fastest corner). When you are constraining unsynchronized inputs and outputs, you use these maximum and minimum numbers for the calculations.

Non-registered GPIO Configuration:
===================================

+----------------------+----------------------+-----------+----------+----------+
|    Instance Name     |       Pin Name       | Parameter | Max (ns) | Min (ns) |
+----------------------+----------------------+-----------+----------+----------+
|       i_arstn        |       i_arstn        |  GPIO_IN  |  1.177   |  0.785   |
|         sw1          |         sw1          |  GPIO_IN  |  1.177   |  0.785   |
...         

For registered blocks, the values correspond to the system timing as observed at the FPGA's pins. The table shows the max (worst) and min (best) values for setup, hold, and clock to output. You use these values to confirm that your system timing requirements are met.

Registered HSIO GPIO Configuration:
====================================

+---------------+----------------+-------+-------+------+------+----------+----------+
| Instance Name |   Clock Pin    |  Max  |  Min  | Max  | Min  |    Max   |    Min   |
                                 | Setup | Setup | Hold | Hold | Clock to | Clock to |
                                 |  (ns) |  (ns) | (ns) | (ns) | Out (ns) | Out (ns) |
+---------------+----------------+-------+-------+------+------+----------+----------+
|   hbc_dq[0]   | i_hbramClk_cal | 0.618 |0.412  |-0.408|-0.272|          |          |
|    hbc_ck_n   | ~i_hbramClk90  |       |       |      |      |  2.226   |  1.484   |
|    hbc_ck_p   | ~i_hbramClk90  |       |       |      |      |  2.226   |  1.484   |
...

The JTAG Timing Report gives the max and min values for the JTAG pins used in your design.

---------- 3. JTAG Timing Report (begin) ----------

+---------------+----------------+-----------+----------+----------+
| Instance Name |    Pin Name    | Parameter | Max (ns) | Min (ns) |
+---------------+----------------+-----------+----------+----------+
|   jtag_inst1  | jtag_inst1_TDI |  JTAG_IN  |  3.164   |  2.109   |
|   jtag_inst1  | jtag_inst1_TMS |  JTAG_IN  |  2.471   |  1.647   |
...