Enhanced String Literals (15.8)

VHDL-2008 enhances bit string literals:
  • They may have an explicit width
  • They may be declared as signed or unsigned
  • They may include meta-values ('U', 'X', etc.)
sig(5 downto 0) <= 6x"0F"  when A(2)        else   --means  6 bit value "001111" 
                   6x"0F"  when A(3)        else   --means "001111"	
                   6Sx"F"  when A(5)        else   --means "111111"     -- sign extension
                   6Ux"F"  when A(6)        else   --means "001111"     -- zero extention
                   6SB"11" when A(7)        else   --means "111111"     -- binary format
                   6uO"7";                         --means "000111"     -- octal format