Inferring Shift Registers

Efinity® synthesis can infer shift register functions that use the XLR cell's 8-bit shift register function. You do not need to set any synthesis options. For example, synthesis infers the following code as a simple shift register:

// 12-bit shift register example
module srl12 (CLK, SI, DO);
input CLK, SI;
output DO;
localparam DATAWIDTH = 12;
reg [DATAWIDTH-1:0] data;

// initializing the shift register content
initial begin
  data = 12'h800;
end

always @(posedge CLK)
  begin
    data <= {data[DATAWIDTH-2:0], data[DATAWIDTH-1]};
  end
assign DO = data[0];

endmodule

The shift register reset is constructed with extra flipflops.

The following example shows a shift register with a reset:

// 12-bit shift register with reset example
module srl12_rst (CLK, DI, RST, DO);
input CLK, DI, RST;
output DO;
localparam DATAWIDTH = 12;
reg [DATAWIDTH-1:0] data;
initial begin
    data = 12'h800;
end

always @(posedge CLK)
 begin
     if (RST) 
        data <= 0;
     else 
        data <= {data[DATAWIDTH-2:0], DI};
 end
assign DO = data[DATAWIDTH-1];

endmodule