async_reg

This attribute applies to register outputs; it designates registers as synchronizers.

When async_reg is true, synthesis does not perform optimization to reduce, merge, or duplicate these registers. During place and route, the software keeps these registers close together to improve synchronization between asynchronous clock domains.

Verilog HDL:

(* async_reg = "true" *) reg [1:0] x;

VHDL:

attribute async_reg: boolean;
attribute async_reg of x : signal is true;