syn_srlstyle

This attribute, when applied to a register signal, directs the synthesis inference step to choose between shift register (srl), simple register (registers), or first register + shift register (reg_srl).

Note: Shift registers are only available in the Titanium family; therefore, you should only use this attribute when targeting Titanium FPGAs.

Verilog HDL:

(* syn_srlstyle = "registers" *) reg [WIDTH-1:0]   d;

VHDL:

attribute syn_srlstyle: string;
attribute syn_srlstyle of d : signal is "registers";