create_generated_clock Constraint

create_generated_clock -source <source clock object> [-divide_by <factor> | \
    -multiply_by <factor>] [-duty_cycle <percentage>] [-invert] \
    [-name <virtual clock name>] <target> [-master_clock <master clock>] \
    [-phase <degree>][-offset <offset value>] \
    [-edges <n1 n2 n3>] [-edge_shift <n1 n2 n3>] \
    [-add]

This constraint is useful for designs with internally generated clock signals because it provides more accurate timing analysis. First, use the create_clock constraint on the source clock that generates the internal clock signal. Then, use this constraint.

-source is the generated clock’s source port, pin, or net.
-divide_by is the division factor.
-multiply_by is the multiplication factor.
-duty_cycle is the duty cycle as a percentage of the clock period.
-invert inverts the clock.
-name is the name of the generated clock.
<target> is the name of the net that implies that it is an internally generated clock signal.
-master_clock specifies the master clock for the generated clock target.
-phase is the phase shift in degrees based on the master clock (the default is 0).
-offset is the absolute time shift in ns relative to the master clock.
-edges is a list of three values that specify the first rising clock edge, the first falling clock edge, and the second rising clock edge for the generate clock's edges as they relate to the edges of the master clock waveform.
-edge_shift is a list of three values that specify the edge shift in ns relative to the edges defined in -edges.
-add defines multiple clocks for the same target. First use -name to specify the new clock name. If you already used the same clock name or did not define it, the last SDC command overwrites the existing clock.

You can use -phase and -offset with the -divide_by, -multiply_by, and -invert options.

You can use -edges and -edge_shift together; however, you cannot use these options with -divide_by, -multiply_by, or -invert.

See Defining Clocks for additional examples.

Tip: The timing analysis and place-and-route runtime is affected by the number of clocks you define in your SDC file. Therefore, if possible, you should only define the most critical clocks to reduce the runtime.

Using -phase and -offset Options

In this example, clkA has a 50% duty cycle and a clock period of 10 ns. The clkA waveform is {0 5}. The divclk waveform is derived from clkA with a divide by 2, resulting in a clock period os 20 ns. With a phase shift of 45 degree, (20 ns * 45) / 360 = 2.5 ns plus a 4 ns offset, resulting in a 6.5 ns shift. The resulting divclk waveform is {6.5 16.5}.

create_clock -period 10 clkA
creage_generated_clock -source [get_ports clkA] -divide_by 2 \
    [get_pins divclk|q] - name divclk -phase 45 -offset 4

Using -edge and -edge_shift Options

In this example, -edge {1 2 3} refers to the first rising_edge, the first falling_edge, and the second rising edge of the generated clock relative to the source clock. In this example, the generated clock's:

First rising edge is the first edge of the source clock
First falling edge is the second edge of the source clock
Second rising edge is the third edge of the source clock

-edge_shift indicates the amount of shifted delay (positive or negative) in ns based on the -edge values.

create_clock -name clkin -period 10 [get_ports clkin]
create_generated_clock -name clkshift -source [get_clocks clkin] \
    -edges {1 2 3} -edge_shift {2.5 0 2.5} [get_ports divclk|Q]

# First rising edge:   0 ns + 2.5 ns = 2.5 ns
# Second rising edge:  5 ns + 0 ns = 5 ns
# Second rising edge:  10 ns + 2.5 ns = 12.5 ns