Input Forward Clock Delay (GPIO output)

This example shows how to set constratints for an input forward clock.

Figure 1. Forward Clock Delay (GPIO Input, Register Bypass)

The SDC constraint formulas for the foward clock delay are:

set_input_delay -clock <clock> -reference_pin <clkout interface name> \
   -max <max calculation> <ports>
set_input_delay -clock <clock> -reference_pin <clkout interface name> \
   -min <min calculation> <ports>

Reference Pin

With forward clocks, you use the -reference_pin option to include the clock latency delay in the I/O constraint. The reference pin target is the pin name of the GPIO output used for the clock.

Constraint Calculation

Calculate the min and max constraints using the following equations:

<max calculation> = <max board constraint> + GPIO_INmax + <GPIO_OUT for clock pad>max

<min calculation> = <min board constraint> + GPIO_INmin + <GPIO_OUT for clock pad>min

The following example shows how to calculate the delays and set the constraints.

Constraining Input Forward Clock

You want to constrain the i input with respect to clock clk_fwd with a max board constraint of 2 ns and a min board constraint of 2 ns. The non-registered GPIO configuration data from the Interface Designer timing report file is:
Non-registered HSIO GPIO Configuration:
========================================
+---------------+----------+-------------+----------+----------+
| Instance Name | Pin Name |  Parameter  | Max (ns) | Min (ns) |
+---------------+----------+-------------+----------+----------+
|      clk      |   clk    | GPIO_CLK_IN |  0.828   |  0.552   |
|       i       |    i     |   GPIO_IN   |  0.828   |  0.552   |
|    clk_fwd    | clk_fwd  |   GPIO_OUT  |  2.205   |  1.470   |
|       o       |    o     |   GPIO_OUT  |  2.205   |  1.470   |
+---------------+----------+-------------+----------+----------+
For <GPIO_OUT for clock pad>, use the GPIO_OUT value for clk_fwd.
The equations are:
<max calculation> = 2 + 0.828 + 2.205 = 5.033
<min calculation> = 2 + 0.552 + 1.470 = 4.022
The reference pin target is the forwarded clock, clk_fwd.
In this example, the RTL is using a divided down clock, divclk, which is only used to drive the clk_fwd signal off chip. Therefore, the set_input_delay constraint is relative to that generated clock. See Example: FPGA Forwarded Clock for a more complete example.
The resulting constraints are:
set_input_delay -clock divclk -reference_pin clk_fwd -max 5.033 [get_ports {i}]
set_input_delay -clock divclk -reference_pin clk_fwd -min 4.022 [get_ports {i}]