Synthesis Options

You can find additional synthesis options for the efx_run script with the efx_map --help option.

efx_map[.exe] --help
Note: Do not run the efx_map application on its own. Use the synthesis options with the efx_run script and the --map_opts option.
Table 1. Synthesis Options
Option Input Description
--help None Show help.
--project Filename Specifies the project XML file name. If empty, the top-level module name is set as the project name.
--project-xml Filename Get the list of source files for synthesis from the project XML file. --v and --f options are ignored.
--work-dir File path Specifies the Efinity working directory path. If unspecified, the default work directory is the current directory.
--output-dir File path Specifies the Efinity output directory path. If unspecified, the default output directory is the current directory.
--max_threads Number Specifies the number of threads to use.
--root Module name Specifies the root module.
--arch VHDL architecture name Specifies the top-level VHDL architecture.
--family Family name Specifies the device family name.
--device Device name Specifies the device name.
--v Filename HDL source files.
--I File path Manage directories where include <directive> will search (--incdir option in Verilog-XL, .hex memory initilization file path resolving).
--f Filename Verilog-XL option to specify a text file containing source file asolute names.
--settings_file Filename Specifies a settings file to be used instead of listing options into the command-line interface.
--write-efx-verilog Filename Specifies an output Verilog HDL file for the mapped netlist.
--binary-db Filename Specifies a Verific binary database file (.vdb) to dump the mapped netlist.
--top-params Parameters List of top module parameters.
--verilog-macros Verilog HDL macros List of Verilog HDL macro definitions.
--max_mult Number Specifies the maximum number of DSP blocks to be inferred.
Default: -1
--max_ram Number Specifies the maximum number of block RAMs to be inferred.
Default: -1
--infer-clk-enable 1, 2, 3, 4 Infer flip-flock clock-enable signals from control logic.
Default: 3
--gated-clk-to-ce 0, 1 Convert gated clock signals into flip-flop clock-enable signals.
Default: 1 (enabled)
--infer-sync-set-reset 0, 1 Infer synchronous set/reset signals for flip-flops from control logic.
Default: 1 (enabled)
--mode speed, area, area2 Synthesis optimization mode.
Default: speed
--fanout-limit Number Set high fanout limit.
Default: 0
--seq_opt 0, 1 Run sequential synthesis.
Default: 1 (enabled)
--message-verbosity 0, 1 Set message printout verbosity.
Default: 0
--retiming 0, 1, 2 Perform register retiming.
0: disabled, 1: enabled (default), 2: advanced mode
--suppress_info_msgs off, on Suppress INFO messages from synthesis.
Default: off
--suppress_warning_​msgs off, on Suppress WARNING messages from synthesis.
Default: off
--msg_suppression_​list Filename File to suppress specific INFO/WARNING messages from synthesis by message IDs.

Using map_opts with a Settings File

efx_run.py helloworld.xml --flow map --map_opts settings_file settings.txt