Debug Wizard
The Debug Wizard provides an automated flow for adding a logic analyzer core to your design. You launch the wizard from the Efinity main icon bar. This wizard is helpful for complex projects with multiple levels of hierarchy. You select signals and nets from the post-map netlist and specifiy the probe type. Then, the wizard automatically creates a debug profile, adds the debug core to your project, connects the nets that you want to debug to the probe ports of the debug instance, and adds the JTAG User Tap block to your interface design. When the wizard completes its processing, you simply compile and start debugging.
Using the Wizard
- Launch the Debug Wizard.
- Choose the buffer depth. The buffer uses on-chip RAM, therefore, a larger buffer uses more RAM.
- Optionally enable capture control. Enabling this option lets you change the capture mode in the Capture Setup tab during debugging (see Debug Perspective for details). If you turn this option on, the logic analyzer uses more FPGA resources.
- Select the JTAG User TAP (USER1 or USER2) to connect to the Debugger in the Connection Settings box.
- In the Signals from list, choose Elaborated Netlist to browse for signals in the pre-map netlist, or Post-Map to use signals from the post-map netlist.
- Select signals and add them using the forward arrows. You can filter the
signal list with regular expressions.Note: Signals with an Undefined clock domain are not driven by any clock in the post-map netlist. If you want to capture the waveform of a signal with an undefined clock domain, you need to manually add the Logic Analyzer core.
- Specify the probe type (Data and Trigger, Data Only, or Trigger Only) for each signal.
- Click Next. The wizard generates the core and hooks it up to your design.
- Turn on Enable Auto Instantiation to have the wizard enable the logic analyzer in your project.
- Click Finish. The Efinity® software saves the debug profile in your project directory as debug_profile.wizard.json. The software also creates a debug template (debug_TEMPLATE.v), which includes the module for the debug profile you created and debug_top.v, which is the RTL logic for the debug core.
JTAG_USER1 or
JTAG_USER2 resource. If you are using the block for the
Debugger, you cannot use it for any other JTAG function; otherwise, you will
receive an error during placement.- Open the Project Editor.
- Click the Debugger tab.
- Select your project's debug_profile.wizard.json in the Debug Profile box.
- Turn on Debugger Auto Instantiation.
Turn off Debugger Auto Instantiation in the Debugger tab to disable the debugger profile.