Simulating

You can use the command line flow to perform RTL simulation on your design’s source files as well as simulation on the post-synthesis netlist file.

Note: In the Efinity software v2024.2 and higher you can also simulate the interface blocks. The supported interfaces blocks are listed in the Trion, Titanium, and Topaz primitives user guides. Simulation support for additional blocks will be available in upcoming releases.

Simulation involves the following steps:

  1. Perform behavioral RTL simulation to ensure that the RTL design matches your testbench functionality. You can include multiple Verilog HDL design files. Use the --flow rtlsim flag.
  2. Run the mapper to synthesize your design using the --flow map flag. The software creates the <project name>.map.v file in the outflow directory, which you use for post-synthesis simulation.
  3. Perform post-map simulation using the top-level testbench and the .map.v file using the --flow mapsim flag.
  4. After generating the interface constraints with the unified netlist option you can simulate the interface logic:
    1. Simulate the core and portion of the interface design defined in the source RTL using the --flow ptsimrtl flag.
    2. Simulate the core design and all of the interface logic defined in the source RTL or the Interface Designer using the --flow ptsimfc flag. This requires a new testbench targeted at the full chip module called <project>~chip.

The following example shows the commands for these three steps:

Simulating at the Command Line

Linux:
efx_run.py <project name>.xml --flow rtlsim
efx_run.py <project name>.xml --flow map
efx_run.py <project name>.xml --flow mapsim
efx_run.py <project name>.xml --flow interface
efx_run.py <project name>.xml --flow ptsimrtl
efx_run.py <project name>.xml --flow ptsimfc
Windows:
efx_run.bat <project name>.xml --flow rtlsim
efx_run.bat <project name>.xml --flow map
efx_run.bat <project name>.xml --flow mapsim
efx_run.bat <project name>.xml --flow interface
efx_run.bat <project name>.xml --flow ptsimrtl
efx_run.bat <project name>.xml --flow ptsimfc

The software saves simulation results into the outflow directory.