Condition Operator (9.2.9)

The software supports the condition operator, as shown in the following code example.

process(ALL) 		-- simplify sensitivity list VHDL 2008; ·
Begin	
	if A(0) then 	-- converts std_logic (A(0)) 1,H to boolean  True, other will be False
		C(0)<='1'
	else 
		C(0)<='0';
	end if;
end process;

C(1) <= '1' when A(1) else '0';