<project>.pt_timing.rpt

In GUI Result pane > Interfaces menu
In file system <project>/outflow
Created by Interface Designer when generating constraints
Design source? No
The Interface Designer creates this file when you generate constraints. This file shows the interface’s timing requirements based on the <project>.pt.sdc. The report has these sections:
  • PLL Timing Report—Shows period and phase shift of output clocks from PLL.
  • GPIO Timing Report—The report shows the following GPIO data:
    • The clock network delay, including the delay from GPIO_GCLK_IN to the core's global network and the delay from the PLL's clkout to GPIO_GCLK_OUT.
    • The output delay for GPIO configured as clock outputs (GPIO_CLK_OUT).
    • The delays for non-registered GPIO.
    • The delays for registered GPIO, including Timing Requirement of both Setup time and Hold time for path from FPGA pins to FPGA interface and the path delay from FPGA interface to FPGA pins.
  • JTAG Timing Report—If you added a debug core to your design, this section shows the JTAG signal delay.