set_max_delay and set_min_delay Constraints

set_max_delay -from <start point> -through <names> -to <end point> <delay> 
set_min_delay -from <start point> -through <names> -to <end point> <delay>

These commands override the default timing constraint (calculated using the information from create_clock) with a user-specified delay. This constraint may produce unexpected results.

  • -to the clock domain destination, I/O, or register end point
  • -from the clock domain destination, I/O, or register end point
  • -through pins, cells, or nets (see -through Option for supported use cases)
  • <start point> is the clock domain source, I/O, or register start point
  • <end point> is the clock domain destination, I/O, or register end point
  • <delay> is the delay value in ns
Important: Using set_min_delay and set_max_delay is a very risky way to close timing because you can mask real setup and hold time violations unintentionally. If you use set_max_delay or set_min_delay to override the default clock-to-clock constraint calculated by the software, the software honors your input and does not give any errors. However, the issue would likely appear on your board as a setup or hold violation. This method is especially risky when used with beneficial skew.