Example Flow

Assume that your design has the following register path: rlock0 to rlock1 to rlock2, and that this path meets timing. We want to constrain this path while we modify another part of the design (that is independent from this constrained path).

To prevent synthesis from optimizing away the registers and wires, use syn_keep in the Verilog HDL design:

(* syn_keep = "true" *) reg rlock0; 
(* syn_keep = "true" *) reg rlock1; 
(* syn_keep = "true" *) reg rlock2; 
(* syn_keep = "true" *) wire rlock0_net; 
(* syn_keep = "true" *) wire rlock1_net; 
(* syn_keep = "true" *) wire rlock2_net;

Run place and route with the options dump_placeloc = on and generate_rcf_template = on. You add these options to a efx_pnr_settings.ini file, one option per line, and save the file in the project folder.
Note: For Trion, add route_dump_constraint_file to the Trion flow and set route_dump_constraint_file = on.
Examine the generated file <project>.out.placeloc to identify the placed location of the locked registers:
```
rlock0~FF 16 49 2 
rlock1~FF 16 50 2 
rlock2~FF 16 44 2
```
Examine the generated file <project>.rcf.template to find the nets between the registers in the .rcf.template file:
```
restoreNetFromTraceFile rlock0_net 
restoreNetFromTraceFile rlock1_net
```
Remove all cells except the locked ones from the <project>.out.placeloc file and save it as your own file called my.placeloc. Similarly, remove all nets except the constrained ones from <project>.rcf.template and save it as your own file called my.rcf file.

Add the following settings to your efx_pnr_setting.ini file:

loc_assignment = my.placeloc 
rcf_file = my.rcf
placer_keepout_file=my.placer_keepout
(Trion) routing_constraint_file= my.route2

You can now modify any other part of the design and re-run the synthesis and place and route. The software constrains the paths you specified.